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lib.memory: thread src_loc_at in {read,write}_port.

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Catherine 2024-03-22 20:49:42 +00:00
parent b8b1e7081b
commit 2640033316
1 changed files with 6 additions and 4 deletions
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10
amaranth/lib/memory.py
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@ -159,7 +159,7 @@ class Memory(wiring.Component):
def attrs(self): def attrs(self):
return self._attrs return self._attrs
def read_port(self, *, domain="sync", transparent_for=()): def read_port(self, *, domain="sync", transparent_for=(), src_loc_at=0):
"""Request a read port. """Request a read port.
If :py:`domain` is :py:`"comb"`, the created read port is asynchronous and always enabled If :py:`domain` is :py:`"comb"`, the created read port is asynchronous and always enabled
@ -185,9 +185,10 @@ class Memory(wiring.Component):
:class:`ReadPort` :class:`ReadPort`
""" """
signature = ReadPort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth)) signature = ReadPort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth))
return ReadPort(signature, memory=self, domain=domain, transparent_for=transparent_for) return ReadPort(signature, memory=self, domain=domain, transparent_for=transparent_for,
src_loc_at=1 + src_loc_at)
def write_port(self, *, domain="sync", granularity=None): def write_port(self, *, domain="sync", granularity=None, src_loc_at=0):
"""Request a write port. """Request a write port.
The created write port is synchronous, updating the contents of the selected row at each The created write port is synchronous, updating the contents of the selected row at each
@ -208,7 +209,8 @@ class Memory(wiring.Component):
""" """
signature = WritePort.Signature( signature = WritePort.Signature(
shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity) shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)
return WritePort(signature, memory=self, domain=domain) return WritePort(signature, memory=self, domain=domain,
src_loc_at=1 + src_loc_at)
# TODO: rename to read_ports # TODO: rename to read_ports
@property @property