vendor.xilinx_{7series,spartan6}: Support extra VHDL files.

nmigen/vendor/xilinx_7series.py

@@ -55,7 +55,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
-            {% for file in platform.iter_extra_files(".v", ".sv") -%}
+            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file}}
             {% endfor %}
             add_files {{name}}.v

nmigen/vendor/xilinx_spartan6.py

@@ -57,6 +57,9 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
+            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+                vhdl work {{file}}
+            {% endfor %}
             {% for file in platform.iter_extra_files(".v") -%}
                 verilog work {{file}}
             {% endfor %}