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hdl.ast: rename nbits to width.

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Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.

This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)

Fixes #210.
This commit is contained in:
whitequark 2019-09-20 15:35:55 +00:00
parent af7224de5d
commit 378e924280
9 changed files with 106 additions and 90 deletions
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6
nmigen/test/test_build_res.py
View file

@ -81,7 +81,7 @@ class ResourceManagerTestCase(FHDLTestCase):
self.assertEqual(len(ports), 2)
scl, sda = ports
self.assertEqual(ports[1].name, "i2c_0__sda__io")
self.assertEqual(ports[1].nbits, 1)
self.assertEqual(ports[1].width, 1)
self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(i2c.scl, scl, {}, False),
@ -102,9 +102,9 @@ class ResourceManagerTestCase(FHDLTestCase):
self.assertEqual(len(ports), 2)
p, n = ports
self.assertEqual(p.name, "clk100_0__p")
self.assertEqual(p.nbits, clk100.width)
self.assertEqual(p.width, clk100.width)
self.assertEqual(n.name, "clk100_0__n")
self.assertEqual(n.nbits, clk100.width)
self.assertEqual(n.width, clk100.width)
self.assertEqual(list(self.cm.iter_differential_pins()), [
(clk100, p, n, {}, False),

4
nmigen/test/test_hdl_ast.py
View file

@ -381,7 +381,7 @@ class SliceTestCase(FHDLTestCase):
class BitSelectTestCase(FHDLTestCase):
def setUp(self):
self.c = Const(0, 8)
self.s = Signal.range(self.c.nbits)
self.s = Signal.range(self.c.width)
def test_shape(self):
s1 = self.c.bit_select(self.s, 2)
@ -405,7 +405,7 @@ class BitSelectTestCase(FHDLTestCase):
class WordSelectTestCase(FHDLTestCase):
def setUp(self):
self.c = Const(0, 8)
self.s = Signal.range(self.c.nbits)
self.s = Signal.range(self.c.width)
def test_shape(self):
s1 = self.c.word_select(self.s, 2)

8
nmigen/test/test_hdl_mem.py
View file

@ -123,8 +123,8 @@ class DummyPortTestCase(FHDLTestCase):
def test_sizes(self):
p1 = DummyPort(width=8, addr_bits=2)
self.assertEqual(p1.addr.nbits, 2)
self.assertEqual(p1.data.nbits, 8)
self.assertEqual(p1.en.nbits, 1)
self.assertEqual(p1.addr.width, 2)
self.assertEqual(p1.data.width, 8)
self.assertEqual(p1.en.width, 1)
p2 = DummyPort(width=8, addr_bits=2, granularity=2)
self.assertEqual(p2.en.nbits, 4)
self.assertEqual(p2.en.width, 4)