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build.res,vendor: place clock constraint on port, not net, if possible.

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For most toolchains, these are functionally identical, although ports
tend to work a bit better, being the common case. For Vivado, though,
it is necessary to place them on the port because its timing analyzer
considers input buffer delay.

Fixes #301.
This commit is contained in:
whitequark 2020-02-06 23:37:15 +00:00
parent 5888f29c1f
commit 3e2ecdf2fb
8 changed files with 70 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

10
nmigen/vendor/intel.py vendored
View file

@ -107,15 +107,19 @@ class IntelPlatform(TemplatedPlatform):
set_global_assignment -name GENERATE_RBF_FILE ON
""",
"{{name}}.sdc": r"""
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("|")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("|")}}]
{% endif %}
{% endfor %}
""",
"{{name}}.srf": r"""
{% for warning in platform.quartus_suppressed_warnings %}
{ "" "" "" "{{name}}.v" { } { } 0 {{warning}} "" 0 0 "Design Software" 0 -1 0 ""}
{% endfor %}
""",
""",
}
command_templates = [
r"""

19
nmigen/vendor/lattice_ecp5.py vendored
View file

@ -135,8 +135,12 @@ class LatticeECP5Platform(TemplatedPlatform):
{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
{% endif %}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
FREQUENCY NET "{{signal|hierarchy(".")}}" {{frequency}} HZ;
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
FREQUENCY PORT "{{port_signal.name}}" {{frequency}} HZ;
{% else -%}
FREQUENCY NET "{{net_signal|hierarchy(".")}}" {{frequency}} HZ;
{% endif %}
{% endfor %}
{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
"""
@ -227,14 +231,15 @@ class LatticeECP5Platform(TemplatedPlatform):
IOBUF PORT "{{port_name}}"
{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ;
{% endfor %}
{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
""",
"{{name}}.sdc": r"""
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""",

12
nmigen/vendor/lattice_ice40.py vendored
View file

@ -134,8 +134,8 @@ class LatticeICE40Platform(TemplatedPlatform):
{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
set_io {{port_name}} {{pin_name}}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
set_frequency {{signal|hierarchy(".")}} {{frequency/1000000}}
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
set_frequency {{net_signal|hierarchy(".")}} {{frequency/1000000}}
{% endfor%}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""",
@ -243,8 +243,12 @@ class LatticeICE40Platform(TemplatedPlatform):
""",
"{{name}}.sdc": r"""
# {{autogenerated}}
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""",

11
nmigen/vendor/lattice_machxo2.py vendored
View file

@ -91,14 +91,15 @@ class LatticeMachXO2Platform(TemplatedPlatform):
{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
{% endif %}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ;
{% endfor %}
{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
""",
"{{name}}.sdc": r"""
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""",

8
nmigen/vendor/xilinx_7series.py vendored
View file

@ -133,8 +133,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
set_property {{attr_name}} {{attr_value}} [get_ports {{port_name}}]
{% endfor %}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
"""

6
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -132,9 +132,9 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
NET "{{port_name}}" {{attr_name}}={{attr_value}};
{% endfor %}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
NET "{{signal|hierarchy("/")}}" TNM_NET="PRD{{signal|hierarchy("/")}}";
TIMESPEC "TS{{signal|hierarchy("/")}}"=PERIOD "PRD{{signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
NET "{{net_signal|hierarchy("/")}}" TNM_NET="PRD{{net_signal|hierarchy("/")}}";
TIMESPEC "TS{{net_signal|hierarchy("/")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
"""

8
nmigen/vendor/xilinx_ultrascale.py vendored
View file

@ -133,8 +133,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
set_property {{attr_name}} {{attr_value}} [get_ports {{port_name}}]
{% endfor %}
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
{% else -%}
create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
"""