vendor.intel: don't use write_verilog -decimal.

See commit 702e41ba for details.

nmigen/vendor/intel.py

@@ -68,15 +68,13 @@ class IntelPlatform(TemplatedPlatform):
             set -e{{verbose("x")}}
             {{emit_commands("sh")}}
         """,
-        # Quartus doesn't like constructs like (* keep = 32'd1 *), even though they mean the same
-        # thing as (* keep = 1 *); use -decimal to work around that.
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_verilog(["-decimal"])}}
+            {{emit_verilog()}}
         """,
         "{{name}}.debug.v": r"""
             /* {{autogenerated}} */
-            {{emit_debug_verilog(["-decimal"])}}
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.qsf": r"""
             # {{autogenerated}}
@@ -146,7 +144,7 @@ class IntelPlatform(TemplatedPlatform):
 
     def add_clock_constraint(self, clock, frequency):
         super().add_clock_constraint(clock, frequency)
-        clock.attrs["keep"] = 1
+        clock.attrs["keep"] = "true"
 
     # The altiobuf_* and altddio_* primitives are explained in the following Intel documents:
     # * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altiobuf.pdf