hdl.ir: detect elaboratables that are created but not used.

Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.

nmigen/lib/cdc.py

@@ -4,7 +4,7 @@ from .. import *
 __all__ = ["MultiReg", "ResetSynchronizer"]
 
 
-class MultiReg:
+class MultiReg(Elaboratable):
     """Resynchronise a signal to a different clock domain.
 
     Consists of a chain of flip-flops. Eliminates metastabilities at the output, but provides
@@ -69,7 +69,7 @@ class MultiReg:
         return m
 
 
-class ResetSynchronizer:
+class ResetSynchronizer(Elaboratable):
     def __init__(self, arst, domain="sync", n=2):
         self.arst = arst
         self.domain = domain

nmigen/lib/coding.py

@@ -10,7 +10,7 @@ __all__ = [
 ]
 
 
-class Encoder:
+class Encoder(Elaboratable):
     """Encode one-hot to binary.
 
     If one bit in ``i`` is asserted, ``n`` is low and ``o`` indicates the asserted bit.
@@ -48,7 +48,7 @@ class Encoder:
         return m
 
 
-class PriorityEncoder:
+class PriorityEncoder(Elaboratable):
     """Priority encode requests to binary.
 
     If any bit in ``i`` is asserted, ``n`` is low and ``o`` indicates the least significant
@@ -85,7 +85,7 @@ class PriorityEncoder:
         return m
 
 
-class Decoder:
+class Decoder(Elaboratable):
     """Decode binary to one-hot.
 
     If ``n`` is low, only the ``i``th bit in ``o`` is asserted.
@@ -130,7 +130,7 @@ class PriorityDecoder(Decoder):
     """
 
 
-class GrayEncoder:
+class GrayEncoder(Elaboratable):
     """Encode binary to Gray code.
 
     Parameters
@@ -157,7 +157,7 @@ class GrayEncoder:
         return m
 
 
-class GrayDecoder:
+class GrayDecoder(Elaboratable):
     """Decode Gray code to binary.
 
     Parameters

nmigen/lib/fifo.py

@@ -102,7 +102,7 @@ def _decr(signal, modulo):
         return Mux(signal == 0, modulo - 1, signal - 1)
 
 
-class SyncFIFO(FIFOInterface):
+class SyncFIFO(Elaboratable, FIFOInterface):
     __doc__ = FIFOInterface._doc_template.format(
     description="""
     Synchronous first in, first out queue.
@@ -209,7 +209,7 @@ class SyncFIFO(FIFOInterface):
         return m
 
 
-class SyncFIFOBuffered(FIFOInterface):
+class SyncFIFOBuffered(Elaboratable, FIFOInterface):
     __doc__ = FIFOInterface._doc_template.format(
     description="""
     Buffered synchronous first in, first out queue.
@@ -265,7 +265,7 @@ class SyncFIFOBuffered(FIFOInterface):
         return m
 
 
-class AsyncFIFO(FIFOInterface):
+class AsyncFIFO(Elaboratable, FIFOInterface):
     __doc__ = FIFOInterface._doc_template.format(
     description="""
     Asynchronous first in, first out queue.
@@ -361,7 +361,7 @@ class AsyncFIFO(FIFOInterface):
         return m
 
 
-class AsyncFIFOBuffered(FIFOInterface):
+class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
     __doc__ = FIFOInterface._doc_template.format(
     description="""
     Buffered asynchronous first in, first out queue.