hdl.mem: use 1 as reset value for ReadPort.en.

This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.

Also, most read ports are always enabled, so this behavior is also
convenient.

nmigen/hdl/mem.py

@@ -88,7 +88,7 @@ class ReadPort(Elaboratable):
         self.data = Signal(memory.width,
                            name="{}_r_data".format(memory.name), src_loc_at=2)
         if self.domain != "comb" and not transparent:
-            self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2)
+            self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2, reset=1)
         else:
             self.en = Const(1)