Initial commit.

examples/alu.py

@@ -0,0 +1,29 @@
+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class ALU:
+    def __init__(self, width):
+        self.sel = Signal(2)
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+        self.co  = Signal()
+
+    def get_fragment(self, platform):
+        f = Module()
+        with f.If(self.sel == 0b00):
+            f.comb += self.o.eq(self.a | self.b)
+        with f.Elif(self.sel == 0b01):
+            f.comb += self.o.eq(self.a & self.b)
+        with f.Elif(self.sel == 0b10):
+            f.comb += self.o.eq(self.a ^ self.b)
+        with f.Else():
+            f.comb += Cat(self.o, self.co).eq(self.a - self.b)
+        return f.lower(platform)
+
+
+alu  = ALU(width=16)
+frag = alu.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))
+print(verilog.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))

examples/alu_hier.py

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+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class Adder:
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.comb += self.o.eq(self.a + self.b)
+        return f.lower(platform)
+
+
+class Subtractor:
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.comb += self.o.eq(self.a - self.b)
+        return f.lower(platform)
+
+
+class ALU:
+    def __init__(self, width):
+        self.op  = Signal()
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+        self.add = Adder(width)
+        self.sub = Subtractor(width)
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.submodules.add = self.add
+        f.submodules.sub = self.sub
+        f.comb += [
+            self.add.a.eq(self.a),
+            self.sub.a.eq(self.a),
+            self.add.b.eq(self.b),
+            self.sub.b.eq(self.b),
+        ]
+        with f.If(self.op):
+            f.comb += self.o.eq(self.sub.o)
+        with f.Else():
+            f.comb += self.o.eq(self.add.o)
+        return f.lower(platform)
+
+
+alu  = ALU(width=16)
+frag = alu.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
+print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o]))

examples/arst.py

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+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class ClockDivisor:
+    def __init__(self, factor):
+        self.v = Signal(factor)
+        self.o = Signal()
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.sync += self.v.eq(self.v + 1)
+        f.comb += self.o.eq(self.v[-1])
+        return f.lower(platform)
+
+
+sys  = ClockDomain(async_reset=True)
+ctr  = ClockDivisor(factor=16)
+frag = ctr.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))
+print(verilog.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))

examples/clkdiv.py

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+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class ClockDivisor:
+    def __init__(self, factor):
+        self.v = Signal(factor, reset=2**factor-1)
+        self.o = Signal()
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.sync += self.v.eq(self.v + 1)
+        f.comb += self.o.eq(self.v[-1])
+        return f.lower(platform)
+
+
+sys  = ClockDomain()
+ctr  = ClockDivisor(factor=16)
+frag = ctr.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[sys.clk, ctr.o], clock_domains={"sys": sys}))
+print(verilog.convert(frag, ports=[sys.clk, ctr.o], clock_domains={"sys": sys}))

examples/ctrl.py

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+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class ClockDivisor:
+    def __init__(self, factor):
+        self.v = Signal(factor, reset=2**factor-1)
+        self.o = Signal()
+        self.ce = Signal()
+
+    def get_fragment(self, platform):
+        f = Module()
+        f.sync += self.v.eq(self.v + 1)
+        f.comb += self.o.eq(self.v[-1])
+        return CEInserter(self.ce)(f.lower())
+
+
+sys  = ClockDomain()
+ctr  = ClockDivisor(factor=16)
+frag = ctr.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
+print(verilog.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))

examples/pmux.py

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+from nmigen.fhdl import *
+from nmigen.back import rtlil, verilog
+
+
+class ParMux:
+    def __init__(self, width):
+        self.s = Signal(3)
+        self.a = Signal(width)
+        self.b = Signal(width)
+        self.c = Signal(width)
+        self.o = Signal(width)
+
+    def get_fragment(self, platform):
+        f = Module()
+        with f.Case(self.s, "--1"):
+            f.comb += self.o.eq(self.a)
+        with f.Case(self.s, "-1-"):
+            f.comb += self.o.eq(self.b)
+        with f.Case(self.s, "1--"):
+            f.comb += self.o.eq(self.c)
+        with f.Case(self.s):
+            f.comb += self.o.eq(0)
+        return f.lower(platform)
+
+
+pmux = ParMux(width=16)
+frag = pmux.get_fragment(platform=None)
+# print(rtlil.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
+print(verilog.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))