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vendor.{_gowin,_lattice_*}: fix DDR buffer naming.

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Wanda 2024-04-10 01:52:14 +02:00 committed by Catherine
parent 545aee7733
commit 4f6b0f23c2
3 changed files with 6 additions and 6 deletions
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4
amaranth/vendor/_gowin.py
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@ -134,7 +134,7 @@ class DDRBuffer(io.DDRBuffer):
i0_inv = Signal(len(self.port)) i0_inv = Signal(len(self.port))
i1_inv = Signal(len(self.port)) i1_inv = Signal(len(self.port))
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.i_ddr = Instance("IDDR", m.submodules[f"i_ddr{bit}"] = Instance("IDDR",
i_CLK=ClockSignal(self.i_domain), i_CLK=ClockSignal(self.i_domain),
i_D=buf.i[bit], i_D=buf.i[bit],
o_Q0=i0_inv[bit], o_Q0=i0_inv[bit],
@ -147,7 +147,7 @@ class DDRBuffer(io.DDRBuffer):
o0_inv = self.o[0] ^ inv_mask o0_inv = self.o[0] ^ inv_mask
o1_inv = self.o[1] ^ inv_mask o1_inv = self.o[1] ^ inv_mask
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.o_ddr = Instance("ODDR", m.submodules[f"o_ddr{bit}"] = Instance("ODDR",
p_TXCLK_POL=0, # default -> Q1 changes on posedge of CLK p_TXCLK_POL=0, # default -> Q1 changes on posedge of CLK
i_CLK=ClockSignal(self.o_domain), i_CLK=ClockSignal(self.o_domain),
i_D0=o0_inv[bit], i_D0=o0_inv[bit],

4
amaranth/vendor/_lattice_ecp5.py
View file

@ -134,7 +134,7 @@ class DDRBuffer(io.DDRBuffer):
i0_inv = Signal(len(self.port)) i0_inv = Signal(len(self.port))
i1_inv = Signal(len(self.port)) i1_inv = Signal(len(self.port))
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.i_ddr = Instance("IDDRX1F", m.submodules[f"i_ddr{bit}"] = Instance("IDDRX1F",
i_SCLK=ClockSignal(self.i_domain), i_SCLK=ClockSignal(self.i_domain),
i_RST=Const(0), i_RST=Const(0),
i_D=buf.i[bit], i_D=buf.i[bit],
@ -152,7 +152,7 @@ class DDRBuffer(io.DDRBuffer):
o1_inv.eq(self.o[1] ^ inv_mask), o1_inv.eq(self.o[1] ^ inv_mask),
] ]
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.o_ddr = Instance("ODDRX1F", m.submodules[f"o_ddr{bit}"] = Instance("ODDRX1F",
i_SCLK=ClockSignal(self.o_domain), i_SCLK=ClockSignal(self.o_domain),
i_RST=Const(0), i_RST=Const(0),
i_D0=o0_inv[bit], i_D0=o0_inv[bit],

4
amaranth/vendor/_lattice_machxo_2_3l.py
View file

@ -21,7 +21,7 @@ class DDRBuffer(io.DDRBuffer):
i0_inv = Signal(len(self.port)) i0_inv = Signal(len(self.port))
i1_inv = Signal(len(self.port)) i1_inv = Signal(len(self.port))
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.i_ddr = Instance("IDDRXE", m.submodules[f"i_ddr{bit}"] = Instance("IDDRXE",
i_SCLK=ClockSignal(self.i_domain), i_SCLK=ClockSignal(self.i_domain),
i_RST=Const(0), i_RST=Const(0),
i_D=buf.i[bit], i_D=buf.i[bit],
@ -39,7 +39,7 @@ class DDRBuffer(io.DDRBuffer):
o1_inv.eq(self.o[1] ^ inv_mask), o1_inv.eq(self.o[1] ^ inv_mask),
] ]
for bit in range(len(self.port)): for bit in range(len(self.port)):
m.submodules.o_ddr = Instance("ODDRXE", m.submodules[f"o_ddr{bit}"] = Instance("ODDRXE",
i_SCLK=ClockSignal(self.o_domain), i_SCLK=ClockSignal(self.o_domain),
i_RST=Const(0), i_RST=Const(0),
i_D0=o0_inv[bit], i_D0=o0_inv[bit],