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test_sim: add failing test case for bitwise binary ops.

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See https://github.com/amaranth-lang/amaranth/pull/826#event-9609577585.
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Charlotte 2023-06-24 13:18:53 +10:00 committed by Catherine
parent 4ec9cbbffe
commit 59a83cf7eb
1 changed files with 9 additions and 0 deletions
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9
tests/test_sim.py
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@ -927,3 +927,12 @@ class SimulatorRegressionTestCase(FHDLTestCase):
r"^Adding a clock process that drives a clock domain object named 'sync', "
r"which is distinct from an identically named domain in the simulated design$"):
sim.add_clock(1e-6, domain=ClockDomain("sync"))
def test_bug_826(self):
sim = Simulator(Module())
def process():
self.assertEqual((yield C(0b0000, 4) | ~C(1, 1)), 0b0000)
self.assertEqual((yield C(0b1111, 4) & ~C(1, 1)), 0b0000)
self.assertEqual((yield C(0b1111, 4) ^ ~C(1, 1)), 0b1111)
sim.add_process(process)
sim.run()