amaranth.hdl: start all private names with an underscore.
This change completes commit 9dc0617e and makes all the tests pass. It corresponds with the ongoing langauge reference documentation effort. Fixes #781.
This commit is contained in:
Catherine
parent
cf83193bf9
commit
5dd1223cf8
34 changed files with 167 additions and 162 deletions
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@ -6,7 +6,7 @@ import re
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from .._utils import flatten
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from ..utils import bits_for
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from ..hdl import ast, ir, mem, xfrm, _repr
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from ..hdl import _ast, _ir, _mem, _xfrm, _repr
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from ..lib import wiring
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@ -27,7 +27,7 @@ def _signed(value):
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return False
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elif isinstance(value, int):
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return value < 0
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elif isinstance(value, ast.Const):
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elif isinstance(value, _ast.Const):
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return value.signed
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else:
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assert False, f"Invalid constant {value!r}"
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@ -43,8 +43,8 @@ def _const(value):
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# This code path is only used for Instances, where Verilog-like behavior is desirable.
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# Verilog ensures that integers with unspecified width are 32 bits wide or more.
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width = max(32, bits_for(value))
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return _const(ast.Const(value, width))
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elif isinstance(value, ast.Const):
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return _const(_ast.Const(value, width))
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elif isinstance(value, _ast.Const):
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value_twos_compl = value.value & ((1 << value.width) - 1)
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return "{}'{:0{}b}".format(value.width, value_twos_compl, value.width)
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else:
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@ -301,12 +301,12 @@ class _LegalizeValue(Exception):
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class _ValueCompilerState:
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def __init__(self, rtlil):
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self.rtlil = rtlil
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self.wires = ast.SignalDict()
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self.driven = ast.SignalDict()
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self.ports = ast.SignalDict()
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self.anys = ast.ValueDict()
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self.wires = _ast.SignalDict()
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self.driven = _ast.SignalDict()
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self.ports = _ast.SignalDict()
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self.anys = _ast.ValueDict()
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self.expansions = ast.ValueDict()
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self.expansions = _ast.ValueDict()
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def add_driven(self, signal, sync):
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self.driven[signal] = sync
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@ -350,7 +350,7 @@ class _ValueCompilerState:
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# For every signal in the sync domain, assign \sig's initial value (using the \init reg
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# attribute) to the reset value.
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if is_sync_driven:
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attrs["init"] = ast.Const(signal.reset, signal.width)
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attrs["init"] = _ast.Const(signal.reset, signal.width)
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wire_curr = self.rtlil.wire(width=signal.width, name=wire_name,
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port_id=port_id, port_kind=port_kind,
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@ -383,7 +383,7 @@ class _ValueCompilerState:
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del self.expansions[value]
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class _ValueCompiler(xfrm.ValueVisitor):
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class _ValueCompiler(_xfrm.ValueVisitor):
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def __init__(self, state):
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self.s = state
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@ -419,7 +419,7 @@ class _ValueCompiler(xfrm.ValueVisitor):
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def on_ArrayProxy(self, value):
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index = self.s.expand(value.index)
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if isinstance(index, ast.Const):
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if isinstance(index, _ast.Const):
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if index.value < len(value.elems):
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elem = value.elems[index.value]
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else:
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@ -523,12 +523,12 @@ class _RHSValueCompiler(_ValueCompiler):
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return res
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def match_shape(self, value, new_shape):
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if isinstance(value, ast.Const):
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return self(ast.Const(value.value, new_shape))
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if isinstance(value, _ast.Const):
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return self(_ast.Const(value.value, new_shape))
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value_shape = value.shape()
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if new_shape.width <= value_shape.width:
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return self(ast.Slice(value, 0, new_shape.width))
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return self(_ast.Slice(value, 0, new_shape.width))
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res = self.s.rtlil.wire(width=new_shape.width, src=_src(value.src_loc))
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self.s.rtlil.cell("$pos", ports={
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@ -548,7 +548,7 @@ class _RHSValueCompiler(_ValueCompiler):
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lhs_wire = self(lhs)
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rhs_wire = self(rhs)
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else:
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lhs_shape = rhs_shape = ast.signed(max(lhs_shape.width + rhs_shape.signed,
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lhs_shape = rhs_shape = _ast.signed(max(lhs_shape.width + rhs_shape.signed,
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rhs_shape.width + lhs_shape.signed))
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lhs_wire = self.match_shape(lhs, lhs_shape)
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rhs_wire = self.match_shape(rhs, rhs_shape)
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@ -570,7 +570,7 @@ class _RHSValueCompiler(_ValueCompiler):
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res = self.s.rtlil.wire(width=res_shape.width, src=_src(value.src_loc))
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self.s.rtlil.cell("$mux", ports={
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"\\A": divmod_res,
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"\\B": self(ast.Const(0, res_shape)),
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"\\B": self(_ast.Const(0, res_shape)),
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"\\S": self(rhs == 0),
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"\\Y": res,
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}, params={
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@ -608,7 +608,7 @@ class _RHSValueCompiler(_ValueCompiler):
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raise TypeError # :nocov:
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def _prepare_value_for_Slice(self, value):
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if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
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if isinstance(value, (_ast.Signal, _ast.Slice, _ast.Cat)):
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sigspec = self(value)
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else:
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sigspec = self.s.rtlil.wire(len(value), src=_src(value.src_loc))
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@ -664,7 +664,7 @@ class _LHSValueCompiler(_ValueCompiler):
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if new_shape.width == value_shape.width:
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return self(value)
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elif new_shape.width < value_shape.width:
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return self(ast.Slice(value, 0, new_shape.width))
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return self(_ast.Slice(value, 0, new_shape.width))
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else: # new_shape.width > value_shape.width
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dummy_bits = new_shape.width - value_shape.width
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dummy_wire = self.s.rtlil.wire(dummy_bits)
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@ -677,15 +677,15 @@ class _LHSValueCompiler(_ValueCompiler):
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return wire_next or wire_curr
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def _prepare_value_for_Slice(self, value):
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assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, ast.Part))
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assert isinstance(value, (_ast.Signal, _ast.Slice, _ast.Cat, _ast.Part))
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return self(value)
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def on_Part(self, value):
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offset = self.s.expand(value.offset)
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if isinstance(offset, ast.Const):
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if isinstance(offset, _ast.Const):
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start = offset.value * value.stride
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stop = start + value.width
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slice = self(ast.Slice(value.value, start, min(len(value.value), stop)))
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slice = self(_ast.Slice(value.value, start, min(len(value.value), stop)))
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if len(value.value) >= stop:
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return slice
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else:
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@ -701,7 +701,7 @@ class _LHSValueCompiler(_ValueCompiler):
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value.src_loc)
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class _StatementCompiler(xfrm.StatementVisitor):
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class _StatementCompiler(_xfrm.StatementVisitor):
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def __init__(self, state, rhs_compiler, lhs_compiler):
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self.state = state
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self.rhs_compiler = rhs_compiler
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@ -780,7 +780,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
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case_src = None
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if values in stmt.case_src_locs:
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case_src = _src(stmt.case_src_locs[values])
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if isinstance(stmt.test, ast.Signal) and stmt.test.decoder:
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if isinstance(stmt.test, _ast.Signal) and stmt.test.decoder:
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decoded_values = []
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for value in values:
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if "-" in value:
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@ -806,7 +806,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
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for branch, test in zip(legalize.branches, tests):
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with self.case(switch, (test,)):
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self._wrap_assign = False
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branch_value = ast.Const(branch, shape)
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branch_value = _ast.Const(branch, shape)
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with self.state.expand_to(legalize.value, branch_value):
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self.on_statement(stmt)
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self._wrap_assign = True
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@ -817,7 +817,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
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def _convert_fragment(builder, fragment, name_map, hierarchy):
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if isinstance(fragment, ir.Instance):
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if isinstance(fragment, _ir.Instance):
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port_map = OrderedDict()
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for port_name, (value, dir) in fragment.named_ports.items():
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port_map[f"\\{port_name}"] = value
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@ -829,10 +829,10 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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else:
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return f"\\{fragment.type}", port_map, params
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if isinstance(fragment, mem.MemoryInstance):
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if isinstance(fragment, _mem.MemoryInstance):
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memory = fragment.memory
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init = "".join(format(ast.Const(elem, ast.unsigned(memory.width)).value, f"0{memory.width}b") for elem in reversed(memory.init))
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init = ast.Const(int(init or "0", 2), memory.depth * memory.width)
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init = "".join(format(_ast.Const(elem, _ast.unsigned(memory.width)).value, f"0{memory.width}b") for elem in reversed(memory.init))
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init = _ast.Const(int(init or "0", 2), memory.depth * memory.width)
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rd_clk = []
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rd_clk_enable = 0
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rd_clk_polarity = 0
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@ -849,7 +849,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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if port.domain == write_port.domain:
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rd_transparency_mask |= 1 << (index * len(fragment.write_ports) + write_index)
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else:
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rd_clk.append(ast.Const(0, 1))
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rd_clk.append(_ast.Const(0, 1))
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wr_clk = []
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wr_clk_enable = 0
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wr_clk_polarity = 0
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@ -863,36 +863,36 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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"MEMID": builder._make_name(hierarchy[-1], local=False),
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"SIZE": memory.depth,
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"OFFSET": 0,
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"ABITS": ast.Shape.cast(range(memory.depth)).width,
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"ABITS": _ast.Shape.cast(range(memory.depth)).width,
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"WIDTH": memory.width,
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"INIT": init,
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"RD_PORTS": len(fragment.read_ports),
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"RD_CLK_ENABLE": ast.Const(rd_clk_enable, max(1, len(fragment.read_ports))),
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"RD_CLK_POLARITY": ast.Const(rd_clk_polarity, max(1, len(fragment.read_ports))),
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"RD_TRANSPARENCY_MASK": ast.Const(rd_transparency_mask, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_COLLISION_X_MASK": ast.Const(0, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_WIDE_CONTINUATION": ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_CE_OVER_SRST": ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_ARST_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_SRST_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_INIT_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_CLK_ENABLE": _ast.Const(rd_clk_enable, max(1, len(fragment.read_ports))),
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"RD_CLK_POLARITY": _ast.Const(rd_clk_polarity, max(1, len(fragment.read_ports))),
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"RD_TRANSPARENCY_MASK": _ast.Const(rd_transparency_mask, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_COLLISION_X_MASK": _ast.Const(0, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_CE_OVER_SRST": _ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_ARST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_SRST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_INIT_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"WR_PORTS": len(fragment.write_ports),
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"WR_CLK_ENABLE": ast.Const(wr_clk_enable, max(1, len(fragment.write_ports))),
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"WR_CLK_POLARITY": ast.Const(wr_clk_polarity, max(1, len(fragment.write_ports))),
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"WR_PRIORITY_MASK": ast.Const(0, max(1, len(fragment.write_ports) * len(fragment.write_ports))),
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"WR_WIDE_CONTINUATION": ast.Const(0, max(1, len(fragment.write_ports))),
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"WR_CLK_ENABLE": _ast.Const(wr_clk_enable, max(1, len(fragment.write_ports))),
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"WR_CLK_POLARITY": _ast.Const(wr_clk_polarity, max(1, len(fragment.write_ports))),
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"WR_PRIORITY_MASK": _ast.Const(0, max(1, len(fragment.write_ports) * len(fragment.write_ports))),
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"WR_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.write_ports))),
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}
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port_map = {
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"\\RD_CLK": ast.Cat(rd_clk),
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"\\RD_EN": ast.Cat(port.en for port in fragment.read_ports),
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"\\RD_ARST": ast.Const(0, len(fragment.read_ports)),
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"\\RD_SRST": ast.Const(0, len(fragment.read_ports)),
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"\\RD_ADDR": ast.Cat(port.addr for port in fragment.read_ports),
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"\\RD_DATA": ast.Cat(port.data for port in fragment.read_ports),
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"\\WR_CLK": ast.Cat(wr_clk),
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"\\WR_EN": ast.Cat(ast.Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in fragment.write_ports),
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"\\WR_ADDR": ast.Cat(port.addr for port in fragment.write_ports),
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"\\WR_DATA": ast.Cat(port.data for port in fragment.write_ports),
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"\\RD_CLK": _ast.Cat(rd_clk),
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"\\RD_EN": _ast.Cat(port.en for port in fragment.read_ports),
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"\\RD_ARST": _ast.Const(0, len(fragment.read_ports)),
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"\\RD_SRST": _ast.Const(0, len(fragment.read_ports)),
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"\\RD_ADDR": _ast.Cat(port.addr for port in fragment.read_ports),
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"\\RD_DATA": _ast.Cat(port.data for port in fragment.read_ports),
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"\\WR_CLK": _ast.Cat(wr_clk),
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"\\WR_EN": _ast.Cat(_ast.Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in fragment.write_ports),
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"\\WR_ADDR": _ast.Cat(port.addr for port in fragment.write_ports),
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"\\WR_DATA": _ast.Cat(port.data for port in fragment.write_ports),
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}
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return "$mem_v2", port_map, params
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@ -931,7 +931,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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# name) names.
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for subfragment, sub_name in fragment.subfragments:
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if not (subfragment.ports or subfragment.statements or subfragment.subfragments or
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isinstance(subfragment, (ir.Instance, mem.MemoryInstance))):
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isinstance(subfragment, (_ir.Instance, _mem.MemoryInstance))):
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# If the fragment is completely empty, skip translating it, otherwise synthesis
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# tools (including Yosys and Vivado) will treat it as a black box when it is
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# loaded after conversion to Verilog.
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@ -946,15 +946,15 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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sub_ports = OrderedDict()
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for port, value in sub_port_map.items():
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if not isinstance(subfragment, (ir.Instance, mem.MemoryInstance)):
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if not isinstance(subfragment, (_ir.Instance, _mem.MemoryInstance)):
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for signal in value._rhs_signals():
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compiler_state.resolve_curr(signal, prefix=sub_name)
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if len(value) > 0 or sub_type == "$mem_v2":
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sub_ports[port] = rhs_compiler(value)
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if isinstance(subfragment, ir.Instance):
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if isinstance(subfragment, _ir.Instance):
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src = _src(subfragment.src_loc)
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elif isinstance(subfragment, mem.MemoryInstance):
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elif isinstance(subfragment, _mem.MemoryInstance):
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src = _src(subfragment.memory.src_loc)
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else:
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src = ""
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@ -969,11 +969,11 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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# Therefore, we translate the fragment as many times as there are independent groups
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# of signals (a group is a transitive closure of signals that appear together on LHS),
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# splitting them into many RTLIL (and thus Verilog) processes.
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lhs_grouper = xfrm.LHSGroupAnalyzer()
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lhs_grouper = _xfrm.LHSGroupAnalyzer()
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lhs_grouper.on_statements(fragment.statements)
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for group, group_signals in lhs_grouper.groups().items():
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lhs_group_filter = xfrm.LHSGroupFilter(group_signals)
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lhs_group_filter = _xfrm.LHSGroupFilter(group_signals)
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group_stmts = lhs_group_filter(fragment.statements)
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with module.process(name=f"$group_{group}") as process:
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@ -985,7 +985,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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if signal not in group_signals:
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continue
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if domain is None:
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prev_value = ast.Const(signal.reset, signal.width)
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prev_value = _ast.Const(signal.reset, signal.width)
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else:
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prev_value = signal
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case.assign(lhs_compiler(signal), rhs_compiler(prev_value))
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@ -1026,8 +1026,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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"\\D": wire_next,
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"\\Q": wire_curr
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}, params={
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"ARST_POLARITY": ast.Const(1),
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"ARST_VALUE": ast.Const(signal.reset, signal.width),
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"ARST_POLARITY": _ast.Const(1),
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"ARST_VALUE": _ast.Const(signal.reset, signal.width),
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"CLK_POLARITY": int(cd.clk_edge == "pos"),
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"WIDTH": signal.width
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})
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@ -1041,7 +1041,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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# alternatives are to add ports for undriven signals (which requires choosing one module
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# to drive it to reset value arbitrarily) or to replace them with their reset value (which
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# removes valuable source location information).
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driven = ast.SignalSet()
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driven = _ast.SignalSet()
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for domain, signals in fragment.iter_drivers():
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driven.update(flatten(signal._lhs_signals() for signal in signals))
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driven.update(fragment.iter_ports(dir="i"))
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@ -1054,7 +1054,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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if wire in driven:
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continue
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wire_curr, _ = compiler_state.wires[wire]
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module.connect(wire_curr, rhs_compiler(ast.Const(wire.reset, wire.width)))
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module.connect(wire_curr, rhs_compiler(_ast.Const(wire.reset, wire.width)))
|
||||
|
||||
# Collect the names we've given to our ports in RTLIL, and correlate these with the signals
|
||||
# represented by these ports. If we are a submodule, this will be necessary to create a cell
|
||||
|
|
@ -1075,9 +1075,9 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
|
|||
|
||||
|
||||
def convert_fragment(fragment, name="top", *, emit_src=True):
|
||||
assert isinstance(fragment, ir.Fragment)
|
||||
assert isinstance(fragment, _ir.Fragment)
|
||||
builder = _Builder(emit_src=emit_src)
|
||||
name_map = ast.SignalDict()
|
||||
name_map = _ast.SignalDict()
|
||||
_convert_fragment(builder, fragment, name_map, hierarchy=(name,))
|
||||
return str(builder), name_map
|
||||
|
||||
|
|
@ -1088,12 +1088,12 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
|
|||
isinstance(elaboratable.signature, wiring.Signature)):
|
||||
ports = []
|
||||
for path, member, value in elaboratable.signature.flatten(elaboratable):
|
||||
if isinstance(value, ast.ValueCastable):
|
||||
if isinstance(value, _ast.ValueCastable):
|
||||
value = value.as_value()
|
||||
if isinstance(value, ast.Value):
|
||||
if isinstance(value, _ast.Value):
|
||||
ports.append(value)
|
||||
elif ports is None:
|
||||
raise TypeError("The `convert()` function requires a `ports=` argument")
|
||||
fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
|
||||
fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
|
||||
il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
|
||||
return il_text
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
from .._toolchain.yosys import *
|
||||
from ..hdl import ast, ir
|
||||
from ..hdl import _ast, _ir
|
||||
from ..lib import wiring
|
||||
from . import rtlil
|
||||
|
||||
|
|
@ -49,12 +49,12 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
|
|||
isinstance(elaboratable.signature, wiring.Signature)):
|
||||
ports = []
|
||||
for path, member, value in elaboratable.signature.flatten(elaboratable):
|
||||
if isinstance(value, ast.ValueCastable):
|
||||
if isinstance(value, _ast.ValueCastable):
|
||||
value = value.as_value()
|
||||
if isinstance(value, ast.Value):
|
||||
if isinstance(value, _ast.Value):
|
||||
ports.append(value)
|
||||
elif ports is None:
|
||||
raise TypeError("The `convert()` function requires a `ports=` argument")
|
||||
fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
|
||||
fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
|
||||
verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
|
||||
return verilog_text
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue