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back.rtlil: explicitly pad constants with zeroes.

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I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
This commit is contained in:
whitequark 2018-12-21 01:51:18 +00:00
parent 221f108fbe
commit 6672ab2e3f
1 changed files with 1 additions and 1 deletions
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2
nmigen/back/rtlil.py
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@ -353,7 +353,7 @@ class _RHSValueCompiler(_ValueCompiler):
if isinstance(value.value, str):
return "{}'{}".format(value.nbits, value.value)
else:
return "{}'{:b}".format(value.nbits, value.value)
return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value)