tests: move out of the main package.

Compared to tests in the repository root, tests in the package have
many downsides:
  * Unless explicitly excluded in find_packages(), tests and their
    support code effectively become a part of public API.
    This, unfortunately, happened with FHDLTestCase, which was never
    intended for downstream use.
  * Even if explicitly excluded from the setuptools package, using
    an editable install, or setting PYTHONPATH still allows accessing
    the tests.
  * Having a sub-package that is present in the source tree but not
    exported (or, worse, exported only sometimes) is confusing.
  * The name `nmigen.test` cannot be used for anything else, such as
    testing utilities that *are* intended for downstream use.

.gitignore

@@ -9,7 +9,7 @@ __pycache__/
 /htmlcov
 
 # tests
-**/test/spec_*/
+/tests/spec_*/
 *.vcd
 *.gtkw
 

setup.py

@@ -48,7 +48,7 @@ setup(
         "builtin-yosys": ["nmigen-yosys>=0.9.*"],
         "remote-build": ["paramiko~=2.7"],
     },
-    packages=find_packages(exclude=["*.test*"]),
+    packages=find_packages(),
     entry_points={
         "console_scripts": [
             "nmigen-rpc = nmigen.rpc:main",

tests/compat/support.py

@@ -1,6 +1,6 @@
-from ..._utils import _ignore_deprecated
-from ...compat import *
-from ...compat.fhdl import verilog
+from nmigen.compat import *
+from nmigen.compat.fhdl import verilog
+from nmigen._utils import _ignore_deprecated
 
 
 class SimCase:

tests/compat/test_coding.py

@@ -2,8 +2,8 @@
 
 import unittest
 
-from ...compat import *
-from ...compat.genlib.coding import *
+from nmigen.compat import *
+from nmigen.compat.genlib.coding import *
 
 from .support import SimCase
 

tests/compat/test_constant.py

@@ -1,6 +1,7 @@
 import unittest
 
-from ...compat import *
+from nmigen.compat import *
+
 from .support import SimCase
 
 

tests/compat/test_fifo.py

@@ -1,8 +1,8 @@
 import unittest
 from itertools import count
 
-from ...compat import *
-from ...compat.genlib.fifo import SyncFIFO
+from nmigen.compat import *
+from nmigen.compat.genlib.fifo import SyncFIFO
 
 from .support import SimCase
 

tests/compat/test_fsm.py

@@ -1,8 +1,8 @@
 import unittest
 from itertools import count
 
-from ...compat import *
-from ...compat.genlib.fsm import FSM
+from nmigen.compat import *
+from nmigen.compat.genlib.fsm import FSM
 
 from .support import SimCase
 

tests/compat/test_passive.py

@@ -1,6 +1,6 @@
 import unittest
 
-from ...compat import *
+from nmigen.compat import *
 
 
 class PassiveCase(unittest.TestCase):

tests/compat/test_run_simulation.py

@@ -1,5 +1,7 @@
 import unittest
-from ... import Signal, Module, Elaboratable
+
+from nmigen import Signal, Module, Elaboratable
+
 from .support import SimCase
 
 

tests/compat/test_signed.py

@@ -1,6 +1,7 @@
 import unittest
 
-from ...compat import *
+from nmigen.compat import *
+
 from .support import SimCase
 
 

tests/compat/test_size.py

@@ -1,7 +1,7 @@
 import unittest
 
-from ..._utils import _ignore_deprecated
-from ...compat import *
+from nmigen._utils import _ignore_deprecated
+from nmigen.compat import *
 
 
 def _same_slices(a, b):

tests/test_build_dsl.py

@@ -1,6 +1,7 @@
 from collections import OrderedDict
 
-from ..build.dsl import *
+from nmigen.build.dsl import *
+
 from .utils import *
 
 

tests/test_build_plat.py

@@ -1,5 +1,6 @@
-from .. import *
-from ..build.plat import *
+from nmigen import *
+from nmigen.build.plat import *
+
 from .utils import *
 
 

tests/test_build_res.py

@@ -1,10 +1,11 @@
 # nmigen: UnusedElaboratable=no
 
-from .. import *
-from ..hdl.rec import *
-from ..lib.io import *
-from ..build.dsl import *
-from ..build.res import *
+from nmigen import *
+from nmigen.hdl.rec import *
+from nmigen.lib.io import *
+from nmigen.build.dsl import *
+from nmigen.build.res import *
+
 from .utils import *
 
 

tests/test_compat.py

@@ -1,5 +1,6 @@
-from ..hdl.ir import Fragment
-from ..compat import *
+from nmigen.hdl.ir import Fragment
+from nmigen.compat import *
+
 from .utils import *
 
 

tests/test_examples.py

@@ -6,7 +6,7 @@ from .utils import *
 
 
 def example_test(name):
-    path = (Path(__file__).parent / ".." / ".." / "examples" / name).resolve()
+    path = (Path(__file__).parent / ".." / "examples" / name).resolve()
     def test_function(self):
         subprocess.check_call([sys.executable, str(path), "generate", "-t", "v"],
                               stdout=subprocess.DEVNULL)
@@ -28,7 +28,6 @@ class ExamplesTestCase(FHDLTestCase):
     test_por        = example_test("basic/por.py")
 
     def test_uart(self):
-        path = (Path(__file__).parent / ".." / ".." / "examples" / "basic" / "uart.py").resolve()
-        def test_function(self):
-            subprocess.check_call([sys.executable, str(path), "generate"],
-                                  stdout=subprocess.DEVNULL)
+        path = (Path(__file__).parent / ".." / "examples" / "basic" / "uart.py").resolve()
+        subprocess.check_call([sys.executable, str(path), "generate"],
+                              stdout=subprocess.DEVNULL)

tests/test_hdl_ast.py

@@ -1,7 +1,8 @@
 import warnings
 from enum import Enum
 
-from ..hdl.ast import *
+from nmigen.hdl.ast import *
+
 from .utils import *
 
 

tests/test_hdl_cd.py

@@ -1,4 +1,5 @@
-from ..hdl.cd import *
+from nmigen.hdl.cd import *
+
 from .utils import *
 
 

tests/test_hdl_dsl.py

@@ -3,9 +3,10 @@
 from collections import OrderedDict
 from enum import Enum
 
-from ..hdl.ast import *
-from ..hdl.cd import *
-from ..hdl.dsl import *
+from nmigen.hdl.ast import *
+from nmigen.hdl.cd import *
+from nmigen.hdl.dsl import *
+
 from .utils import *
 
 

tests/test_hdl_ir.py

@@ -2,10 +2,11 @@
 
 from collections import OrderedDict
 
-from ..hdl.ast import *
-from ..hdl.cd import *
-from ..hdl.ir import *
-from ..hdl.mem import *
+from nmigen.hdl.ast import *
+from nmigen.hdl.cd import *
+from nmigen.hdl.ir import *
+from nmigen.hdl.mem import *
+
 from .utils import *
 
 

tests/test_hdl_mem.py

@@ -1,7 +1,8 @@
 # nmigen: UnusedElaboratable=no
 
-from ..hdl.ast import *
-from ..hdl.mem import *
+from nmigen.hdl.ast import *
+from nmigen.hdl.mem import *
+
 from .utils import *
 
 

tests/test_hdl_rec.py

@@ -1,7 +1,8 @@
 from enum import Enum
 
-from ..hdl.ast import *
-from ..hdl.rec import *
+from nmigen.hdl.ast import *
+from nmigen.hdl.rec import *
+
 from .utils import *
 
 

tests/test_hdl_xfrm.py

@@ -1,10 +1,11 @@
 # nmigen: UnusedElaboratable=no
 
-from ..hdl.ast import *
-from ..hdl.cd import *
-from ..hdl.ir import *
-from ..hdl.xfrm import *
-from ..hdl.mem import *
+from nmigen.hdl.ast import *
+from nmigen.hdl.cd import *
+from nmigen.hdl.ir import *
+from nmigen.hdl.xfrm import *
+from nmigen.hdl.mem import *
+
 from .utils import *
 
 

tests/test_lib_cdc.py

@@ -1,9 +1,10 @@
 # nmigen: UnusedElaboratable=no
 
+from nmigen.hdl import *
+from nmigen.back.pysim import *
+from nmigen.lib.cdc import *
+
 from .utils import *
-from ..hdl import *
-from ..back.pysim import *
-from ..lib.cdc import *
 
 
 class FFSynchronizerTestCase(FHDLTestCase):

tests/test_lib_coding.py

@@ -1,8 +1,9 @@
+from nmigen.hdl import *
+from nmigen.asserts import *
+from nmigen.back.pysim import *
+from nmigen.lib.coding import *
+
 from .utils import *
-from ..hdl import *
-from ..asserts import *
-from ..back.pysim import *
-from ..lib.coding import *
 
 
 class EncoderTestCase(FHDLTestCase):

tests/test_lib_fifo.py

@@ -1,10 +1,11 @@
 # nmigen: UnusedElaboratable=no
 
+from nmigen.hdl import *
+from nmigen.asserts import *
+from nmigen.back.pysim import *
+from nmigen.lib.fifo import *
+
 from .utils import *
-from ..hdl import *
-from ..asserts import *
-from ..back.pysim import *
-from ..lib.fifo import *
 
 
 class FIFOTestCase(FHDLTestCase):

tests/test_lib_io.py

@@ -1,8 +1,9 @@
+from nmigen.hdl import *
+from nmigen.hdl.rec import *
+from nmigen.back.pysim import *
+from nmigen.lib.io import *
+
 from .utils import *
-from ..hdl import *
-from ..hdl.rec import *
-from ..back.pysim import *
-from ..lib.io import *
 
 
 class PinLayoutTestCase(FHDLTestCase):

tests/test_lib_scheduler.py

@@ -1,10 +1,13 @@
 # nmigen: UnusedElaboratable=no
+
 import unittest
+
+from nmigen.hdl import *
+from nmigen.asserts import *
+from nmigen.sim.pysim import *
+from nmigen.lib.scheduler import *
+
 from .utils import *
-from ..hdl import *
-from ..asserts import *
-from ..sim.pysim import *
-from ..lib.scheduler import *
 
 
 class RoundRobinTestCase(unittest.TestCase):

tests/test_sim.py

@@ -1,15 +1,16 @@
 import os
 from contextlib import contextmanager
 
+from nmigen._utils import flatten, union
+from nmigen.hdl.ast import *
+from nmigen.hdl.cd import  *
+from nmigen.hdl.mem import *
+from nmigen.hdl.rec import *
+from nmigen.hdl.dsl import  *
+from nmigen.hdl.ir import *
+from nmigen.back.pysim import *
+
 from .utils import *
-from .._utils import flatten, union
-from ..hdl.ast import *
-from ..hdl.cd import  *
-from ..hdl.mem import *
-from ..hdl.rec import *
-from ..hdl.dsl import  *
-from ..hdl.ir import *
-from ..back.pysim import *
 
 
 class SimulatorUnitTestCase(FHDLTestCase):

tests/utils.py

@@ -5,13 +5,12 @@ import subprocess
 import textwrap
 import traceback
 import unittest
-import warnings
 from contextlib import contextmanager
 
-from ..hdl.ast import *
-from ..hdl.ir import *
-from ..back import rtlil
-from .._toolchain import require_tool
+from nmigen.hdl.ast import *
+from nmigen.hdl.ir import *
+from nmigen.back import rtlil
+from nmigen._toolchain import require_tool
 
 
 __all__ = ["FHDLTestCase"]