67b957d4f4
Compared to tests in the repository root, tests in the package have
many downsides:
* Unless explicitly excluded in find_packages(), tests and their
support code effectively become a part of public API.
This, unfortunately, happened with FHDLTestCase, which was never
intended for downstream use.
* Even if explicitly excluded from the setuptools package, using
an editable install, or setting PYTHONPATH still allows accessing
the tests.
* Having a sub-package that is present in the source tree but not
exported (or, worse, exported only sometimes) is confusing.
* The name `nmigen.test` cannot be used for anything else, such as
testing utilities that *are* intended for downstream use.
97 lines
3.1 KiB
Python
97 lines
3.1 KiB
Python
# nmigen: UnusedElaboratable=no
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import unittest
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from nmigen.hdl import *
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from nmigen.asserts import *
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from nmigen.sim.pysim import *
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from nmigen.lib.scheduler import *
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from .utils import *
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class RoundRobinTestCase(unittest.TestCase):
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def test_count(self):
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dut = RoundRobin(count=32)
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self.assertEqual(dut.count, 32)
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self.assertEqual(len(dut.requests), 32)
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self.assertEqual(len(dut.grant), 5)
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def test_wrong_count(self):
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not 'foo'"):
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dut = RoundRobin(count="foo")
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not -1"):
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dut = RoundRobin(count=-1)
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class RoundRobinSimulationTestCase(unittest.TestCase):
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def test_count_one(self):
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dut = RoundRobin(count=1)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(1)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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def test_transitions(self):
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dut = RoundRobin(count=3)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0b111)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b110)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b010)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b011)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b101)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b100)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b000)
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yield; yield Delay(1e-8)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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