vendor._lattice_ice40: implement lib.io buffer primitives.
This commit is contained in:
Wanda
Catherine
parent
4e3550db43
commit
6857daff54
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@ -2,6 +2,7 @@ from abc import abstractmethod
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from ..hdl import *
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from ..lib.cdc import ResetSynchronizer
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from ..lib import io
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from ..build import *
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@ -414,206 +415,162 @@ class LatticeICE40Platform(TemplatedPlatform):
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return m
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def should_skip_port_component(self, port, attrs, component):
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
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# the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
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return True
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return False
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def _get_io_buffer(self, m, pin, port, attrs, *, i_invert=False, o_invert=False,
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invert_lut=False):
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def get_dff(clk, d, q):
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def _get_io_buffer_single(self, buffer, port, *, invert_lut=False):
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def get_dff(domain, q, d):
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for bit in range(len(d)):
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m.submodules += Instance("SB_DFF",
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i_C=clk,
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i_C=ClockSignal(domain),
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i_D=d[bit],
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o_Q=q[bit])
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def get_ineg(y, invert):
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def get_inv(y, a):
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if invert_lut:
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a = Signal.like(y, name_suffix=f"_x{1 if invert else 0}")
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for bit in range(len(y)):
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for bit, inv in enumerate(port.invert):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
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p_LUT_INIT=Const(0b01 if inv else 0b10, 16),
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return a
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elif invert:
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a = Signal.like(y, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return a
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else:
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return y
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mask = sum(int(inv) << bit for bit, inv in enumerate(port.invert))
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if mask == 0:
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m.d.comb += y.eq(a)
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elif mask == ((1 << len(port)) - 1):
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m.d.comb += y.eq(~a)
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else:
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m.d.comb += y.eq(a ^ mask)
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def get_oneg(a, invert):
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if invert_lut:
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y = Signal.like(a, name_suffix=f"_x{1 if invert else 0}")
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for bit in range(len(a)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return y
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elif invert:
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y = Signal.like(a, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return y
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else:
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return a
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m = Module()
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if "GLOBAL" in attrs:
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is_global_input = bool(attrs["GLOBAL"])
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del attrs["GLOBAL"]
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if isinstance(buffer, io.DDRBuffer):
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if buffer.direction is not io.Direction.Output:
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# Re-register both inputs before they enter fabric. This increases hold time
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# to an entire cycle, and adds one cycle of latency.
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i0 = Signal(len(port))
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i1 = Signal(len(port))
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i0_neg = Signal(len(port))
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i1_neg = Signal(len(port))
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get_inv(i0_neg, i0)
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get_inv(i1_neg, i1)
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get_dff(buffer.i_domain, buffer.i[0], i0_neg)
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get_dff(buffer.i_domain, buffer.i[1], i1_neg)
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if buffer.direction is not io.Direction.Input:
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# Re-register negedge output after it leaves fabric. This increases setup time
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# to an entire cycle, and doesn't add latency.
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o0 = Signal(len(port))
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o1 = Signal(len(port))
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o1_ff = Signal(len(port))
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get_dff(buffer.o_domain, o1_ff, buffer.o[1])
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get_inv(o0, buffer.o[0])
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get_inv(o1, o1_ff)
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else:
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is_global_input = False
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assert not (is_global_input and i_invert)
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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if "i" in pin.dir and pin.xdr == 2:
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i0_ff = Signal.like(pin_i0, name_suffix="_ff")
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i1_ff = Signal.like(pin_i1, name_suffix="_ff")
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get_dff(pin.i_clk, i0_ff, pin_i0)
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get_dff(pin.i_clk, i1_ff, pin_i1)
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if "o" in pin.dir and pin.xdr == 2:
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o1_ff = Signal.like(pin_o1, name_suffix="_ff")
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get_dff(pin.o_clk, pin_o1, o1_ff)
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if buffer.direction is not io.Direction.Output:
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i = Signal(len(port))
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get_inv(buffer.i, i)
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if buffer.direction is not io.Direction.Input:
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o = Signal(len(port))
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get_inv(o, buffer.o)
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for bit in range(len(port)):
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attrs = port.io.metadata[bit].attrs
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is_global_input = bool(attrs.get("GLOBAL", False))
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if buffer.direction is io.Direction.Output:
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is_global_input = False
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if is_global_input:
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if port.invert[bit]:
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raise ValueError("iCE40 global input buffer doesn't support inversion")
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if not isinstance(buffer, io.Buffer):
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raise ValueError("iCE40 global input buffer cannot be registered")
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io_args = [
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("io", "PACKAGE_PIN", port[bit]),
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*(("p", key, value) for key, value in attrs.items()),
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("io", "PACKAGE_PIN", port.io[bit]),
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*(("p", key, value) for key, value in attrs.items() if key != "GLOBAL"),
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]
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if "i" not in pin.dir:
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if buffer.direction is io.Direction.Output:
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# If no input pin is requested, it is important to use a non-registered input pin
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# type, because an output-only pin would not have an input clock, and if its input
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# is configured as registered, this would prevent a co-located input-capable pin
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# from using an input clock.
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i_type = 0b01 # PIN_INPUT
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elif pin.xdr == 0:
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elif isinstance(buffer, io.Buffer):
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i_type = 0b01 # PIN_INPUT
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elif pin.xdr > 0:
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if is_global_input:
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io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", i[bit]))
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else:
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io_args.append(("o", "D_IN_0", i[bit]))
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elif isinstance(buffer, io.FFBuffer):
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i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
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if "o" not in pin.dir:
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io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain)))
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io_args.append(("o", "D_IN_0", i[bit]))
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elif isinstance(buffer, io.DDRBuffer):
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i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
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io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain)))
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io_args.append(("o", "D_IN_0", i0[bit]))
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io_args.append(("o", "D_IN_1", i1[bit]))
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if buffer.direction is io.Direction.Input:
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o_type = 0b0000 # PIN_NO_OUTPUT
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elif pin.xdr == 0 and pin.dir == "o":
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o_type = 0b0110 # PIN_OUTPUT
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elif pin.xdr == 0:
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elif isinstance(buffer, io.Buffer):
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o_type = 0b1010 # PIN_OUTPUT_TRISTATE
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elif pin.xdr == 1 and pin.dir == "o":
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o_type = 0b0101 # PIN_OUTPUT_REGISTERED
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elif pin.xdr == 1:
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io_args.append(("i", "D_OUT_0", o[bit]))
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elif isinstance(buffer, io.FFBuffer):
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o_type = 0b1101 # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
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elif pin.xdr == 2 and pin.dir == "o":
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o_type = 0b0100 # PIN_OUTPUT_DDR
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elif pin.xdr == 2:
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io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain)))
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io_args.append(("i", "D_OUT_0", o[bit]))
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elif isinstance(buffer, io.DDRBuffer):
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o_type = 0b1100 # PIN_OUTPUT_DDR_ENABLE_REGISTERED
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io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain)))
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io_args.append(("i", "D_OUT_0", o0[bit]))
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io_args.append(("i", "D_OUT_1", o1[bit]))
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io_args.append(("p", "PIN_TYPE", C((o_type << 2) | i_type, 6)))
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if hasattr(pin, "i_clk"):
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io_args.append(("i", "INPUT_CLK", pin.i_clk))
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if hasattr(pin, "o_clk"):
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io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
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if "i" in pin.dir:
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if pin.xdr == 0 and is_global_input:
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io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
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elif pin.xdr < 2:
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io_args.append(("o", "D_IN_0", pin_i[bit]))
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elif pin.xdr == 2:
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# Re-register both inputs before they enter fabric. This increases hold time
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# to an entire cycle, and adds one cycle of latency.
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io_args.append(("o", "D_IN_0", i0_ff[bit]))
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io_args.append(("o", "D_IN_1", i1_ff[bit]))
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if "o" in pin.dir:
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if pin.xdr < 2:
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io_args.append(("i", "D_OUT_0", pin_o[bit]))
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elif pin.xdr == 2:
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# Re-register negedge output after it leaves fabric. This increases setup time
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# to an entire cycle, and doesn't add latency.
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io_args.append(("i", "D_OUT_0", pin_o0[bit]))
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io_args.append(("i", "D_OUT_1", o1_ff[bit]))
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if pin.dir in ("oe", "io"):
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io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
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if buffer.direction is not io.Direction.Input:
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io_args.append(("i", "OUTPUT_ENABLE", buffer.oe))
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if is_global_input:
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m.submodules[f"{pin.name}_{bit}"] = Instance("SB_GB_IO", *io_args)
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m.submodules[f"buf{bit}"] = Instance("SB_GB_IO", *io_args)
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else:
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m.submodules[f"{pin.name}_{bit}"] = Instance("SB_IO", *io_args)
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m.submodules[f"buf{bit}"] = Instance("SB_IO", *io_args)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert, o_invert=invert)
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return m
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def get_diff_input(self, pin, port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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# See comment in should_skip_port_component above.
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self._get_io_buffer(m, pin, port.p, attrs, i_invert=invert)
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return m
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def get_diff_output(self, pin, port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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# Note that the non-inverting output pin is not driven the same way as a regular
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# output pin. The inverter introduces a delay, so for a non-inverting output pin,
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# an identical delay is introduced by instantiating a LUT. This makes the waveform
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# perfectly symmetric in the xdr=0 case.
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self._get_io_buffer(m, pin, port.p, attrs, o_invert= invert, invert_lut=True)
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self._get_io_buffer(m, pin, port.n, attrs, o_invert=not invert, invert_lut=True)
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return m
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# Tristate bidirectional buffers are not supported on iCE40 because it requires external
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# termination, which is different for differential pins configured as inputs and outputs.
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def get_io_buffer(self, buffer):
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if not isinstance(buffer, (io.Buffer, io.FFBuffer, io.DDRBuffer)):
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raise TypeError(f"Unknown IO buffer type {buffer!r}")
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if isinstance(buffer.port, io.DifferentialPort):
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port_p = io.SingleEndedPort(buffer.port.p, invert=buffer.port.invert,
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direction=buffer.port.direction)
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port_n = ~io.SingleEndedPort(buffer.port.n, invert=buffer.port.invert,
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direction=buffer.port.direction)
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if buffer.direction is io.Direction.Bidir:
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# Tristate bidirectional buffers are not supported on iCE40 because it requires
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# external termination, which is different for differential pins configured
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# as inputs and outputs.
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raise TypeError("iCE40 does not support bidirectional differential ports")
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elif buffer.direction is io.Direction.Output:
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m = Module()
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invert_lut = isinstance(buffer, io.Buffer)
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m.submodules.p = self._get_io_buffer_single(buffer, port_p, invert_lut=invert_lut)
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m.submodules.n = self._get_io_buffer_single(buffer, port_n, invert_lut=invert_lut)
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return m
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elif buffer.direction is io.Direction.Input:
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive
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# for the pin with z=0, which is the non-inverting pin. The pinout unfortunately
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# differs between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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return self._get_io_buffer_single(buffer, port_p, invert_lut=invert_lut)
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else:
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assert False # :nocov:
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elif isinstance(buffer.port, io.SingleEndedPort):
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return self._get_io_buffer_single(buffer, buffer.port)
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else:
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raise TypeError(f"Unknown port type {buffer.port!r}")
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# CDC primitives are not currently specialized for iCE40. It is not known if iCECube2 supports
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# the necessary attributes; nextpnr-ice40 does not.
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