lib.memory: Memory.{r,w}_ports
→.{read,write}_ports
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The abbreviated form was initially added to match `lib.fifo`, but it looks very out of place on `lib.memory`, and we may be moving away from such heavy use of abbreviations anyway. While technically a breaking change, these attributes have very narrow usefulness and so this change qualifies as "minor".
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@ -207,18 +207,16 @@ class Memory(wiring.Component):
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return WritePort(signature, memory=self, domain=domain,
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return WritePort(signature, memory=self, domain=domain,
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src_loc_at=1 + src_loc_at)
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src_loc_at=1 + src_loc_at)
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# TODO: rename to read_ports
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@property
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@property
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def r_ports(self):
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def read_ports(self):
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"""All read ports defined so far.
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"""All read ports defined so far.
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This property is provided for the :py:`platform.get_memory()` override.
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This property is provided for the :py:`platform.get_memory()` override.
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"""
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"""
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return tuple(self._read_ports)
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return tuple(self._read_ports)
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# TODO: rename to write_ports
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@property
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@property
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def w_ports(self):
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def write_ports(self):
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"""All write ports defined so far.
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"""All write ports defined so far.
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This property is provided for the :py:`platform.get_memory()` override.
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This property is provided for the :py:`platform.get_memory()` override.
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@ -131,9 +131,9 @@ Memories
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.. automethod:: write_port
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.. automethod:: write_port
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.. autoproperty:: r_ports
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.. autoproperty:: read_ports
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.. autoproperty:: w_ports
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.. autoproperty:: write_ports
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Memory ports
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Memory ports
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@ -121,7 +121,7 @@ class WritePortTestCase(FHDLTestCase):
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m = memory.Memory(depth=16, shape=8, init=[])
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m = memory.Memory(depth=16, shape=8, init=[])
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port = memory.WritePort(signature, memory=m, domain="sync")
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port = memory.WritePort(signature, memory=m, domain="sync")
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self.assertIs(port.memory, m)
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self.assertIs(port.memory, m)
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self.assertEqual(m.w_ports, (port,))
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self.assertEqual(m.write_ports, (port,))
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signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4)
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signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4)
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port = signature.create()
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port = signature.create()
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@ -228,7 +228,7 @@ class ReadPortTestCase(FHDLTestCase):
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m = memory.Memory(depth=16, shape=8, init=[])
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m = memory.Memory(depth=16, shape=8, init=[])
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port = memory.ReadPort(signature, memory=m, domain="sync")
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port = memory.ReadPort(signature, memory=m, domain="sync")
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self.assertIs(port.memory, m)
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self.assertIs(port.memory, m)
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self.assertEqual(m.r_ports, (port,))
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self.assertEqual(m.read_ports, (port,))
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write_port = m.write_port()
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write_port = m.write_port()
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port = memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[write_port])
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port = memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[write_port])
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self.assertIs(port.memory, m)
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self.assertIs(port.memory, m)
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@ -291,8 +291,8 @@ class MemoryTestCase(FHDLTestCase):
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self.assertEqual(list(m.init), [1, 2, 3, 0])
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self.assertEqual(list(m.init), [1, 2, 3, 0])
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self.assertEqual(m.init._raw, [1, 2, 3, 0])
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self.assertEqual(m.init._raw, [1, 2, 3, 0])
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self.assertRepr(m.init, "Memory.Init([1, 2, 3, 0], shape=8, depth=4)")
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self.assertRepr(m.init, "Memory.Init([1, 2, 3, 0], shape=8, depth=4)")
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self.assertEqual(m.r_ports, ())
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self.assertEqual(m.read_ports, ())
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self.assertEqual(m.w_ports, ())
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self.assertEqual(m.write_ports, ())
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def test_constructor_shapecastable(self):
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def test_constructor_shapecastable(self):
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init = [
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init = [
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@ -375,8 +375,8 @@ class MemoryTestCase(FHDLTestCase):
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wp = m.write_port()
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wp = m.write_port()
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self.assertEqual(wp.signature.addr_width, addr_width)
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self.assertEqual(wp.signature.addr_width, addr_width)
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self.assertEqual(wp.signature.shape, 8)
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self.assertEqual(wp.signature.shape, 8)
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self.assertEqual(m.r_ports, (rp,))
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self.assertEqual(m.read_ports, (rp,))
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self.assertEqual(m.w_ports, (wp,))
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self.assertEqual(m.write_ports, (wp,))
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def test_elaborate(self):
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def test_elaborate(self):
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m = memory.Memory(shape=MyStruct, depth=4, init=[{"a": 1, "b": 2}])
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m = memory.Memory(shape=MyStruct, depth=4, init=[{"a": 1, "b": 2}])
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