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back.pysim: implement sim.add_clock(if_exists=True).

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This commit is contained in:
whitequark 2019-08-23 08:53:48 +00:00
parent 906385c7f8
commit 72cf4ca991
2 changed files with 13 additions and 5 deletions
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9
nmigen/back/pysim.py
View file

@ -438,7 +438,7 @@ class Simulator:
sync_process = sync_process()
self.add_process(sync_process)
def add_clock(self, period, phase=None, domain="sync"):
def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
if domain in self._all_clocks:
@ -453,8 +453,11 @@ class Simulator:
clk = domain_obj.clk
break
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
if if_exists:
return
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
def clk_process():
yield Passive()
yield Delay(phase)

9
nmigen/test/test_sim.py
View file

@ -403,7 +403,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
"a generator function"):
sim.add_process(1)
def test_add_clock_wrong(self):
def test_add_clock_wrong_twice(self):
m = Module()
s = Signal()
m.d.sync += s.eq(0)
@ -413,13 +413,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1)
def test_add_clock_wrong(self):
def test_add_clock_wrong_missing(self):
m = Module()
with self.assertSimulation(m) as sim:
with self.assertRaises(ValueError,
msg="Domain 'sync' is not present in simulation"):
sim.add_clock(1)
def test_add_clock_if_exists(self):
m = Module()
with self.assertSimulation(m) as sim:
sim.add_clock(1, if_exists=True)
def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs()
self.s = Signal()