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back.pysim: implement sim.add_clock(if_exists=True).

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This commit is contained in:
whitequark 2019-08-23 08:53:48 +00:00
parent 906385c7f8
commit 72cf4ca991
2 changed files with 13 additions and 5 deletions
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9
nmigen/back/pysim.py
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@ -438,7 +438,7 @@ class Simulator:
sync_process = sync_process()
self.add_process(sync_process)
def add_clock(self, period, phase=None, domain="sync"):
def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
if domain in self._all_clocks:
@ -453,8 +453,11 @@ class Simulator:
clk = domain_obj.clk
break
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
if if_exists:
return
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
def clk_process():
yield Passive()
yield Delay(phase)