hdl: remove deprecated Sample, Past, Stable, Rose, Fell.
This commit is contained in:
Catherine
parent
475b0f35dd
commit
750cbbc3c7
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@ -1,2 +1,4 @@
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from .hdl.ast import AnyConst, AnySeq, Assert, Assume, Cover
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from .hdl.ast import Past, Stable, Rose, Fell, Initial
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from .hdl.ast import AnyConst, AnySeq, Initial, Assert, Assume, Cover
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__all__ = ["AnyConst", "AnySeq", "Initial", "Assert", "Assume", "Cover"]
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@ -398,12 +398,6 @@ class _ValueCompiler(xfrm.ValueVisitor):
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Sample(self, value):
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raise NotImplementedError # :nocov:
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def on_Initial(self, value):
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raise NotImplementedError # :nocov:
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def on_Cat(self, value):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.parts])))
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@ -498,6 +492,13 @@ class _RHSValueCompiler(_ValueCompiler):
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self.s.anys[value] = res
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return res
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def on_Initial(self, value):
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res = self.s.rtlil.wire(width=1, src=_src(value.src_loc))
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self.s.rtlil.cell("$initstate", ports={
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"\\Y": res,
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}, src=_src(value.src_loc))
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return res
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def on_Signal(self, value):
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wire_curr, wire_next = self.s.resolve(value)
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return wire_curr
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@ -646,6 +647,9 @@ class _LHSValueCompiler(_ValueCompiler):
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def on_AnySeq(self, value):
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raise TypeError # :nocov:
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def on_Initial(self, value):
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raise TypeError # :nocov:
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def on_Operator(self, value):
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if value.operator in ("u", "s"):
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# These operators are transparent on the LHS.
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@ -9,7 +9,7 @@ import jinja2
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from .. import __version__
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from .._toolchain import *
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from ..hdl import *
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from ..hdl.xfrm import SampleLowerer, DomainLowerer
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from ..hdl.xfrm import DomainLowerer
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from ..lib.cdc import ResetSynchronizer
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from ..back import rtlil, verilog
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from .res import *
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@ -143,7 +143,6 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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self._prepared = True
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fragment = Fragment.get(elaboratable, self)
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fragment = SampleLowerer()(fragment)
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fragment._propagate_domains(self.create_missing_domain, platform=self)
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fragment = DomainLowerer()(fragment)
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@ -20,7 +20,7 @@ __all__ = [
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"Array", "ArrayProxy",
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"Signal", "ClockSignal", "ResetSignal",
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"ValueCastable", "ValueLike",
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"Sample", "Past", "Stable", "Rose", "Fell", "Initial",
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"Initial",
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"Statement", "Switch",
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"Property", "Assign", "Assert", "Assume", "Cover",
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"ValueKey", "ValueDict", "ValueSet", "SignalKey", "SignalDict", "SignalSet",
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@ -1549,70 +1549,6 @@ class ValueLike(metaclass=_ValueLikeMeta):
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raise TypeError("ValueLike is an abstract class and cannot be constructed")
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# TODO(amaranth-0.5): remove
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@final
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class Sample(Value):
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"""Value from the past.
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A ``Sample`` of an expression is equal to the value of the expression ``clocks`` clock edges
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of the ``domain`` clock back. If that moment is before the beginning of time, it is equal
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to the value of the expression calculated as if each signal had its reset value.
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"""
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@deprecated("instead of using `Sample`, create a register explicitly")
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def __init__(self, expr, clocks, domain, *, src_loc_at=0):
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super().__init__(src_loc_at=1 + src_loc_at)
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self.value = Value.cast(expr)
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self.clocks = int(clocks)
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self.domain = domain
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if not isinstance(self.value, (Const, Signal, ClockSignal, ResetSignal, Initial)):
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raise TypeError("Sampled value must be a signal or a constant, not {!r}"
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.format(self.value))
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if self.clocks < 0:
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raise ValueError("Cannot sample a value {} cycles in the future"
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.format(-self.clocks))
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if not (self.domain is None or isinstance(self.domain, str)):
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raise TypeError("Domain name must be a string or None, not {!r}"
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.format(self.domain))
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def shape(self):
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return self.value.shape()
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def _rhs_signals(self):
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return SignalSet((self,))
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def __repr__(self):
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return "(sample {!r} @ {}[{}])".format(
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self.value, "<default>" if self.domain is None else self.domain, self.clocks)
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# TODO(amaranth-0.5): remove
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@deprecated("instead of using `Past`, create a register explicitly")
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def Past(expr, clocks=1, domain=None):
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with _ignore_deprecated():
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return Sample(expr, clocks, domain)
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# TODO(amaranth-0.5): remove
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@deprecated("instead of using `Stable`, create registers and comparisons explicitly")
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def Stable(expr, clocks=0, domain=None):
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with _ignore_deprecated():
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return Sample(expr, clocks + 1, domain) == Sample(expr, clocks, domain)
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# TODO(amaranth-0.5): remove
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@deprecated("instead of using `Rose`, create registers and comparisons explicitly")
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def Rose(expr, clocks=0, domain=None):
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with _ignore_deprecated():
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return ~Sample(expr, clocks + 1, domain) & Sample(expr, clocks, domain)
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# TODO(amaranth-0.5): remove
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@deprecated("instead of using `Fell`, create registers and comparisons explicitly")
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def Fell(expr, clocks=0, domain=None):
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with _ignore_deprecated():
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return Sample(expr, clocks + 1, domain) & ~Sample(expr, clocks, domain)
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@final
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class Initial(Value):
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"""Start indicator, for model checking.
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@ -1626,7 +1562,7 @@ class Initial(Value):
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return Shape(1)
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def _rhs_signals(self):
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return SignalSet((self,))
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return SignalSet()
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def __repr__(self):
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return "(initial)"
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@ -1895,8 +1831,6 @@ class ValueKey:
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elif isinstance(self.value, ArrayProxy):
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self._hash = hash((ValueKey(self.value.index),
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tuple(ValueKey(e) for e in self.value._iter_as_values())))
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elif isinstance(self.value, Sample):
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self._hash = hash((ValueKey(self.value.value), self.value.clocks, self.value.domain))
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elif isinstance(self.value, Initial):
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self._hash = 0
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else: # :nocov:
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@ -1942,10 +1876,6 @@ class ValueKey:
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all(ValueKey(a) == ValueKey(b)
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for a, b in zip(self.value._iter_as_values(),
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other.value._iter_as_values())))
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elif isinstance(self.value, Sample):
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return (ValueKey(self.value.value) == ValueKey(other.value.value) and
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self.value.clocks == other.value.clocks and
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self.value.domain == self.value.domain)
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elif isinstance(self.value, Initial):
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return True
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else: # :nocov:
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@ -491,7 +491,6 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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.format(domain_name(domain)))
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stmt._MustUse__used = True
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stmt = SampleDomainInjector(domain)(stmt)
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for signal in stmt._lhs_signals():
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if signal not in self._driving:
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@ -539,8 +538,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
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for submodule in self._anon_submodules:
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fragment.add_subfragment(Fragment.get(submodule, platform), None)
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statements = SampleDomainInjector("sync")(self._statements)
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fragment.add_statements(statements)
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fragment.add_statements(self._statements)
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for signal, domain in self._driving.items():
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fragment.add_driver(signal, domain)
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fragment.add_domains(self._domains.values())
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@ -506,11 +506,10 @@ class Fragment:
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self.add_ports(sig, dir="i")
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def prepare(self, ports=None, missing_domain=lambda name: ClockDomain(name)):
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from .xfrm import SampleLowerer, DomainLowerer
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from .xfrm import DomainLowerer
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fragment = SampleLowerer()(self)
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new_domains = fragment._propagate_domains(missing_domain)
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fragment = DomainLowerer()(fragment)
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new_domains = self._propagate_domains(missing_domain)
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fragment = DomainLowerer()(self)
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if ports is None:
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fragment._propagate_ports(ports=(), all_undef_as_ports=True)
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else:
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@ -15,7 +15,6 @@ __all__ = ["ValueVisitor", "ValueTransformer",
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"FragmentTransformer",
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"TransformedElaboratable",
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"DomainCollector", "DomainRenamer", "DomainLowerer",
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"SampleDomainInjector", "SampleLowerer",
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"SwitchCleaner", "LHSGroupAnalyzer", "LHSGroupFilter",
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"ResetInserter", "EnableInserter"]
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@ -65,10 +64,6 @@ class ValueVisitor(metaclass=ABCMeta):
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def on_ArrayProxy(self, value):
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pass # :nocov:
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@abstractmethod
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def on_Sample(self, value):
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pass # :nocov:
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@abstractmethod
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def on_Initial(self, value):
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pass # :nocov:
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@ -103,8 +98,6 @@ class ValueVisitor(metaclass=ABCMeta):
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new_value = self.on_Cat(value)
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elif type(value) is ArrayProxy:
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new_value = self.on_ArrayProxy(value)
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elif type(value) is Sample:
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new_value = self.on_Sample(value)
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elif type(value) is Initial:
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new_value = self.on_Initial(value)
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else:
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@ -153,9 +146,6 @@ class ValueTransformer(ValueVisitor):
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return ArrayProxy([self.on_value(elem) for elem in value._iter_as_values()],
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self.on_value(value.index))
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def on_Sample(self, value):
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return Sample(self.on_value(value.value), value.clocks, value.domain)
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def on_Initial(self, value):
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return value
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@ -369,9 +359,6 @@ class DomainCollector(ValueVisitor, StatementVisitor):
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self.on_value(elem)
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self.on_value(value.index)
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def on_Sample(self, value):
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self.on_value(value.value)
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def on_Initial(self, value):
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pass
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@ -509,81 +496,6 @@ class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
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return new_fragment
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class SampleDomainInjector(ValueTransformer, StatementTransformer):
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def __init__(self, domain):
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self.domain = domain
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@_ignore_deprecated
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def on_Sample(self, value):
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if value.domain is not None:
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return value
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return Sample(value.value, value.clocks, self.domain)
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def __call__(self, stmts):
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return self.on_statement(stmts)
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class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer):
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def __init__(self):
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self.initial = None
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self.sample_cache = None
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self.sample_stmts = None
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def _name_reset(self, value):
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if isinstance(value, Const):
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return f"c${value.value}", value.value
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elif isinstance(value, Signal):
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return f"s${value.name}", value.reset
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elif isinstance(value, ClockSignal):
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return "clk", 0
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elif isinstance(value, ResetSignal):
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return "rst", 1
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elif isinstance(value, Initial):
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return "init", 0 # Past(Initial()) produces 0, 1, 0, 0, ...
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else:
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raise NotImplementedError # :nocov:
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@_ignore_deprecated
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def on_Sample(self, value):
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if value in self.sample_cache:
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return self.sample_cache[value]
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sampled_value = self.on_value(value.value)
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if value.clocks == 0:
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sample = sampled_value
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else:
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assert value.domain is not None
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sampled_name, sampled_reset = self._name_reset(value.value)
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name = f"$sample${sampled_name}${value.domain}${value.clocks}"
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sample = Signal.like(value.value, name=name, reset_less=True, reset=sampled_reset)
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sample.attrs["amaranth.sample_reg"] = True
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prev_sample = self.on_Sample(Sample(sampled_value, value.clocks - 1, value.domain))
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if value.domain not in self.sample_stmts:
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self.sample_stmts[value.domain] = []
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self.sample_stmts[value.domain].append(sample.eq(prev_sample))
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self.sample_cache[value] = sample
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return sample
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def on_Initial(self, value):
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if self.initial is None:
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self.initial = Signal(name="init")
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return self.initial
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def map_statements(self, fragment, new_fragment):
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self.initial = None
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self.sample_cache = ValueDict()
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self.sample_stmts = OrderedDict()
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new_fragment.add_statements(map(self.on_statement, fragment.statements))
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for domain, stmts in self.sample_stmts.items():
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new_fragment.add_statements(stmts)
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for stmt in stmts:
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new_fragment.add_driver(stmt.lhs, domain)
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if self.initial is not None:
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new_fragment.add_subfragment(Instance("$initstate", o_Y=self.initial))
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class SwitchCleaner(StatementVisitor):
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def on_ignore(self, stmt):
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return stmt
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@ -103,9 +103,6 @@ class _ValueCompiler(ValueVisitor, _Compiler):
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def on_AnySeq(self, value):
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raise NotImplementedError # :nocov:
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def on_Sample(self, value):
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raise NotImplementedError # :nocov:
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def on_Initial(self, value):
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raise NotImplementedError # :nocov:
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@ -13,6 +13,7 @@ Language changes
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.. currentmodule:: amaranth.hdl
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* Removed: (deprecated in 0.4) :meth:`Const.normalize`. (`RFC 5`_)
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* Removed: (deprecated in 0.4) :class:`ast.Sample`, :class:`ast.Past`, :class:`ast.Stable`, :class:`ast.Rose`, :class:`ast.Fell`.
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Standard library changes
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@ -894,7 +894,7 @@ class CatTestCase(FHDLTestCase):
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def test_cast(self):
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c = Cat(1, 0)
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self.assertEqual(repr(c), "(cat (const 1'd1) (const 1'd0))")
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def test_str_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Object 'foo' cannot be converted to an Amaranth value$"):
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@ -1382,39 +1382,6 @@ class ValueLikeTestCase(FHDLTestCase):
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self.assertFalse(isinstance(EnumD.A, ValueLike))
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class SampleTestCase(FHDLTestCase):
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@_ignore_deprecated
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def test_const(self):
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s = Sample(1, 1, "sync")
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self.assertEqual(s.shape(), unsigned(1))
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@_ignore_deprecated
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def test_signal(self):
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s1 = Sample(Signal(2), 1, "sync")
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self.assertEqual(s1.shape(), unsigned(2))
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s2 = Sample(ClockSignal(), 1, "sync")
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s3 = Sample(ResetSignal(), 1, "sync")
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@_ignore_deprecated
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def test_wrong_value_operator(self):
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with self.assertRaisesRegex(TypeError,
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(r"^Sampled value must be a signal or a constant, not "
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r"\(\+ \(sig \$signal\) \(const 1'd1\)\)$")):
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Sample(Signal() + 1, 1, "sync")
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@_ignore_deprecated
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def test_wrong_clocks_neg(self):
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with self.assertRaisesRegex(ValueError,
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r"^Cannot sample a value 1 cycles in the future$"):
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Sample(Signal(), -1, "sync")
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@_ignore_deprecated
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def test_wrong_domain(self):
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with self.assertRaisesRegex(TypeError,
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r"^Domain name must be a string or None, not 0$"):
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Sample(Signal(), 1, 0)
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class InitialTestCase(FHDLTestCase):
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def test_initial(self):
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i = Initial()
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@ -133,25 +133,6 @@ class DSLTestCase(FHDLTestCase):
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)
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""")
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@_ignore_deprecated
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def test_sample_domain(self):
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m = Module()
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i = Signal()
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o1 = Signal()
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o2 = Signal()
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o3 = Signal()
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m.d.sync += o1.eq(Past(i))
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m.d.pix += o2.eq(Past(i))
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m.d.pix += o3.eq(Past(i, domain="sync"))
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f = m.elaborate(platform=None)
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self.assertRepr(f.statements, """
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(
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(eq (sig o1) (sample (sig i) @ sync[1]))
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(eq (sig o2) (sample (sig i) @ pix[1]))
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(eq (sig o3) (sample (sig i) @ sync[1]))
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)
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""")
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def test_If(self):
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m = Module()
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with m.If(self.s1):
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@ -210,54 +210,6 @@ class DomainLowererTestCase(FHDLTestCase):
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DomainLowerer()(f)
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class SampleLowererTestCase(FHDLTestCase):
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def setUp(self):
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self.i = Signal()
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||||
self.o1 = Signal()
|
||||
self.o2 = Signal()
|
||||
self.o3 = Signal()
|
||||
|
||||
@_ignore_deprecated
|
||||
def test_lower_signal(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.o1.eq(Sample(self.i, 2, "sync")),
|
||||
self.o2.eq(Sample(self.i, 1, "sync")),
|
||||
self.o3.eq(Sample(self.i, 1, "pix")),
|
||||
)
|
||||
|
||||
f = SampleLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
(
|
||||
(eq (sig o1) (sig $sample$s$i$sync$2))
|
||||
(eq (sig o2) (sig $sample$s$i$sync$1))
|
||||
(eq (sig o3) (sig $sample$s$i$pix$1))
|
||||
(eq (sig $sample$s$i$sync$1) (sig i))
|
||||
(eq (sig $sample$s$i$sync$2) (sig $sample$s$i$sync$1))
|
||||
(eq (sig $sample$s$i$pix$1) (sig i))
|
||||
)
|
||||
""")
|
||||
self.assertEqual(len(f.drivers["sync"]), 2)
|
||||
self.assertEqual(len(f.drivers["pix"]), 1)
|
||||
|
||||
@_ignore_deprecated
|
||||
def test_lower_const(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.o1.eq(Sample(1, 2, "sync")),
|
||||
)
|
||||
|
||||
f = SampleLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
(
|
||||
(eq (sig o1) (sig $sample$c$1$sync$2))
|
||||
(eq (sig $sample$c$1$sync$1) (const 1'd1))
|
||||
(eq (sig $sample$c$1$sync$2) (sig $sample$c$1$sync$1))
|
||||
)
|
||||
""")
|
||||
self.assertEqual(len(f.drivers["sync"]), 2)
|
||||
|
||||
|
||||
class SwitchCleanerTestCase(FHDLTestCase):
|
||||
def test_clean(self):
|
||||
a = Signal()
|
||||
|
|
|
|||
|
|
@ -911,53 +911,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
|
||||
@_ignore_deprecated
|
||||
def test_sample_helpers(self):
|
||||
m = Module()
|
||||
s = Signal(2)
|
||||
def mk(x):
|
||||
y = Signal.like(x)
|
||||
m.d.comb += y.eq(x)
|
||||
return y
|
||||
p0, r0, f0, s0 = mk(Past(s, 0)), mk(Rose(s)), mk(Fell(s)), mk(Stable(s))
|
||||
p1, r1, f1, s1 = mk(Past(s)), mk(Rose(s, 1)), mk(Fell(s, 1)), mk(Stable(s, 1))
|
||||
p2, r2, f2, s2 = mk(Past(s, 2)), mk(Rose(s, 2)), mk(Fell(s, 2)), mk(Stable(s, 2))
|
||||
p3, r3, f3, s3 = mk(Past(s, 3)), mk(Rose(s, 3)), mk(Fell(s, 3)), mk(Stable(s, 3))
|
||||
with self.assertSimulation(m) as sim:
|
||||
def process_gen():
|
||||
yield s.eq(0b10)
|
||||
yield
|
||||
yield
|
||||
yield s.eq(0b01)
|
||||
yield
|
||||
def process_check():
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
self.assertEqual((yield p0), 0b01)
|
||||
self.assertEqual((yield p1), 0b10)
|
||||
self.assertEqual((yield p2), 0b10)
|
||||
self.assertEqual((yield p3), 0b00)
|
||||
|
||||
self.assertEqual((yield s0), 0b0)
|
||||
self.assertEqual((yield s1), 0b1)
|
||||
self.assertEqual((yield s2), 0b0)
|
||||
self.assertEqual((yield s3), 0b1)
|
||||
|
||||
self.assertEqual((yield r0), 0b01)
|
||||
self.assertEqual((yield r1), 0b00)
|
||||
self.assertEqual((yield r2), 0b10)
|
||||
self.assertEqual((yield r3), 0b00)
|
||||
|
||||
self.assertEqual((yield f0), 0b10)
|
||||
self.assertEqual((yield f1), 0b00)
|
||||
self.assertEqual((yield f2), 0b00)
|
||||
self.assertEqual((yield f3), 0b00)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process_gen)
|
||||
sim.add_sync_process(process_check)
|
||||
|
||||
def test_vcd_wrong_nonzero_time(self):
|
||||
s = Signal()
|
||||
m = Module()
|
||||
|
|
|
|||
Loading…
Reference in a new issue