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hdl: remove deprecated Sample, Past, Stable, Rose, Fell.

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This commit is contained in:
Catherine 2023-11-25 00:38:33 +00:00
parent 475b0f35dd
commit 750cbbc3c7
13 changed files with 23 additions and 328 deletions
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35
tests/test_hdl_ast.py
View file

@ -894,7 +894,7 @@ class CatTestCase(FHDLTestCase):
def test_cast(self):
c = Cat(1, 0)
self.assertEqual(repr(c), "(cat (const 1'd1) (const 1'd0))")
def test_str_wrong(self):
with self.assertRaisesRegex(TypeError,
r"^Object 'foo' cannot be converted to an Amaranth value$"):
@ -1382,39 +1382,6 @@ class ValueLikeTestCase(FHDLTestCase):
self.assertFalse(isinstance(EnumD.A, ValueLike))
class SampleTestCase(FHDLTestCase):
@_ignore_deprecated
def test_const(self):
s = Sample(1, 1, "sync")
self.assertEqual(s.shape(), unsigned(1))
@_ignore_deprecated
def test_signal(self):
s1 = Sample(Signal(2), 1, "sync")
self.assertEqual(s1.shape(), unsigned(2))
s2 = Sample(ClockSignal(), 1, "sync")
s3 = Sample(ResetSignal(), 1, "sync")
@_ignore_deprecated
def test_wrong_value_operator(self):
with self.assertRaisesRegex(TypeError,
(r"^Sampled value must be a signal or a constant, not "
r"\(\+ \(sig \$signal\) \(const 1'd1\)\)$")):
Sample(Signal() + 1, 1, "sync")
@_ignore_deprecated
def test_wrong_clocks_neg(self):
with self.assertRaisesRegex(ValueError,
r"^Cannot sample a value 1 cycles in the future$"):
Sample(Signal(), -1, "sync")
@_ignore_deprecated
def test_wrong_domain(self):
with self.assertRaisesRegex(TypeError,
r"^Domain name must be a string or None, not 0$"):
Sample(Signal(), 1, 0)
class InitialTestCase(FHDLTestCase):
def test_initial(self):
i = Initial()

19
tests/test_hdl_dsl.py
View file

@ -133,25 +133,6 @@ class DSLTestCase(FHDLTestCase):
)
""")
@_ignore_deprecated
def test_sample_domain(self):
m = Module()
i = Signal()
o1 = Signal()
o2 = Signal()
o3 = Signal()
m.d.sync += o1.eq(Past(i))
m.d.pix += o2.eq(Past(i))
m.d.pix += o3.eq(Past(i, domain="sync"))
f = m.elaborate(platform=None)
self.assertRepr(f.statements, """
(
(eq (sig o1) (sample (sig i) @ sync[1]))
(eq (sig o2) (sample (sig i) @ pix[1]))
(eq (sig o3) (sample (sig i) @ sync[1]))
)
""")
def test_If(self):
m = Module()
with m.If(self.s1):

48
tests/test_hdl_xfrm.py
View file

@ -210,54 +210,6 @@ class DomainLowererTestCase(FHDLTestCase):
DomainLowerer()(f)
class SampleLowererTestCase(FHDLTestCase):
def setUp(self):
self.i = Signal()
self.o1 = Signal()
self.o2 = Signal()
self.o3 = Signal()
@_ignore_deprecated
def test_lower_signal(self):
f = Fragment()
f.add_statements(
self.o1.eq(Sample(self.i, 2, "sync")),
self.o2.eq(Sample(self.i, 1, "sync")),
self.o3.eq(Sample(self.i, 1, "pix")),
)
f = SampleLowerer()(f)
self.assertRepr(f.statements, """
(
(eq (sig o1) (sig $sample$s$i$sync$2))
(eq (sig o2) (sig $sample$s$i$sync$1))
(eq (sig o3) (sig $sample$s$i$pix$1))
(eq (sig $sample$s$i$sync$1) (sig i))
(eq (sig $sample$s$i$sync$2) (sig $sample$s$i$sync$1))
(eq (sig $sample$s$i$pix$1) (sig i))
)
""")
self.assertEqual(len(f.drivers["sync"]), 2)
self.assertEqual(len(f.drivers["pix"]), 1)
@_ignore_deprecated
def test_lower_const(self):
f = Fragment()
f.add_statements(
self.o1.eq(Sample(1, 2, "sync")),
)
f = SampleLowerer()(f)
self.assertRepr(f.statements, """
(
(eq (sig o1) (sig $sample$c$1$sync$2))
(eq (sig $sample$c$1$sync$1) (const 1'd1))
(eq (sig $sample$c$1$sync$2) (sig $sample$c$1$sync$1))
)
""")
self.assertEqual(len(f.drivers["sync"]), 2)
class SwitchCleanerTestCase(FHDLTestCase):
def test_clean(self):
a = Signal()

47
tests/test_sim.py
View file

@ -911,53 +911,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6)
sim.add_sync_process(process)
@_ignore_deprecated
def test_sample_helpers(self):
m = Module()
s = Signal(2)
def mk(x):
y = Signal.like(x)
m.d.comb += y.eq(x)
return y
p0, r0, f0, s0 = mk(Past(s, 0)), mk(Rose(s)), mk(Fell(s)), mk(Stable(s))
p1, r1, f1, s1 = mk(Past(s)), mk(Rose(s, 1)), mk(Fell(s, 1)), mk(Stable(s, 1))
p2, r2, f2, s2 = mk(Past(s, 2)), mk(Rose(s, 2)), mk(Fell(s, 2)), mk(Stable(s, 2))
p3, r3, f3, s3 = mk(Past(s, 3)), mk(Rose(s, 3)), mk(Fell(s, 3)), mk(Stable(s, 3))
with self.assertSimulation(m) as sim:
def process_gen():
yield s.eq(0b10)
yield
yield
yield s.eq(0b01)
yield
def process_check():
yield
yield
yield
self.assertEqual((yield p0), 0b01)
self.assertEqual((yield p1), 0b10)
self.assertEqual((yield p2), 0b10)
self.assertEqual((yield p3), 0b00)
self.assertEqual((yield s0), 0b0)
self.assertEqual((yield s1), 0b1)
self.assertEqual((yield s2), 0b0)
self.assertEqual((yield s3), 0b1)
self.assertEqual((yield r0), 0b01)
self.assertEqual((yield r1), 0b00)
self.assertEqual((yield r2), 0b10)
self.assertEqual((yield r3), 0b00)
self.assertEqual((yield f0), 0b10)
self.assertEqual((yield f1), 0b00)
self.assertEqual((yield f2), 0b00)
self.assertEqual((yield f3), 0b00)
sim.add_clock(1e-6)
sim.add_sync_process(process_gen)
sim.add_sync_process(process_check)
def test_vcd_wrong_nonzero_time(self):
s = Signal()
m = Module()