sim: {add,remove}_trigger
→{add,remove}_signal_trigger
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parent
eef248a080
commit
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@ -52,10 +52,10 @@ class BaseSimulation:
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slots = NotImplemented
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slots = NotImplemented
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def add_trigger(self, process, signal, *, trigger=None):
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def add_signal_trigger(self, process, signal, *, trigger=None):
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raise NotImplementedError # :nocov:
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raise NotImplementedError # :nocov:
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def remove_trigger(self, process, signal):
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def remove_signal_trigger(self, process, signal):
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raise NotImplementedError # :nocov:
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raise NotImplementedError # :nocov:
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def add_memory_trigger(self, process, memory):
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def add_memory_trigger(self, process, memory):
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@ -42,12 +42,12 @@ class PyCoroProcess(BaseProcess):
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return f"{inspect.getfile(frame)}:{inspect.getlineno(frame)}"
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return f"{inspect.getfile(frame)}:{inspect.getlineno(frame)}"
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def add_trigger(self, signal, trigger=None):
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def add_trigger(self, signal, trigger=None):
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self.state.add_trigger(self, signal, trigger=trigger)
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self.state.add_signal_trigger(self, signal, trigger=trigger)
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self.waits_on.add(signal)
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self.waits_on.add(signal)
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def clear_triggers(self):
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def clear_triggers(self):
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for signal in self.waits_on:
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for signal in self.waits_on:
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self.state.remove_trigger(self, signal)
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self.state.remove_signal_trigger(self, signal)
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self.waits_on.clear()
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self.waits_on.clear()
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def run(self):
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def run(self):
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@ -501,15 +501,15 @@ class _FragmentCompiler:
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lhs(port._data)(data)
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lhs(port._data)(data)
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for input in inputs:
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for input in inputs:
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self.state.add_trigger(domain_process, input)
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self.state.add_signal_trigger(domain_process, input)
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else:
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else:
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domain = fragment.domains[domain_name]
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domain = fragment.domains[domain_name]
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clk_trigger = 1 if domain.clk_edge == "pos" else 0
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clk_trigger = 1 if domain.clk_edge == "pos" else 0
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self.state.add_trigger(domain_process, domain.clk, trigger=clk_trigger)
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self.state.add_signal_trigger(domain_process, domain.clk, trigger=clk_trigger)
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if domain.rst is not None and domain.async_reset:
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if domain.rst is not None and domain.async_reset:
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rst_trigger = 1
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rst_trigger = 1
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self.state.add_trigger(domain_process, domain.rst, trigger=rst_trigger)
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self.state.add_signal_trigger(domain_process, domain.rst, trigger=rst_trigger)
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for signal in domain_signals:
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for signal in domain_signals:
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signal_index = self.state.get_signal(signal)
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signal_index = self.state.get_signal(signal)
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@ -476,13 +476,13 @@ class _PySimulation(BaseSimulation):
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self.memories[memory] = index
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self.memories[memory] = index
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return index
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return index
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def add_trigger(self, process, signal, *, trigger=None):
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def add_signal_trigger(self, process, signal, *, trigger=None):
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index = self.get_signal(signal)
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index = self.get_signal(signal)
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assert (process not in self.slots[index].waiters or
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assert (process not in self.slots[index].waiters or
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self.slots[index].waiters[process] == trigger)
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self.slots[index].waiters[process] == trigger)
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self.slots[index].waiters[process] = trigger
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self.slots[index].waiters[process] = trigger
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def remove_trigger(self, process, signal):
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def remove_signal_trigger(self, process, signal):
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index = self.get_signal(signal)
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index = self.get_signal(signal)
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assert process in self.slots[index].waiters
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assert process in self.slots[index].waiters
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del self.slots[index].waiters[process]
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del self.slots[index].waiters[process]
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