back.pysim: redesign the simulator.

The redesign introduces no fundamental incompatibilities, but it does
involve minor breaking changes:
  * The simulator commands were moved from hdl.ast to back.pysim
    (instead of only being reexported from back.pysim).
  * back.pysim.DeadlineError was removed.

Summary of changes:
  * The new simulator compiles HDL to Python code and is >6x faster.
    (The old one compiled HDL to lots of Python lambdas.)
  * The new simulator is a straightforward, rigorous implementation
    of the Synchronous Reactive Programming paradigm, instead of
    a pile of ad-hoc code with no particular design driving it.
  * The new simulator never raises DeadlineError, and there is no
    limit on the amount of delta cycles.
  * The new simulator robustly handles multiclock designs.
  * The new simulator can be reset, such that the compiled design
    can be reused, which can save significant runtime with large
    designs.
  * Generators can no longer be added as processes, since that would
    break reset(); only generator functions may be. If necessary,
    they may be added by wrapping them into a generator function;
    a deprecated fallback does just that. This workaround will raise
    an exception if the simulator is reset and restarted.
  * The new simulator does not depend on Python extensions.
    (The old one required bitarray, which did not provide wheels.)

Fixes #28.
Fixes #34.
Fixes #160.
Fixes #161.
Fixes #215.
Fixes #242.
Fixes #262.

nmigen/compat/sim/__init__.py

@@ -21,15 +21,24 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
         generators = {"sync": generators}
         fragment.domains += ClockDomain("sync")
 
-    with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
-        for domain, period in clocks.items():
-            sim.add_clock(period / 1e9, domain=domain)
-        for domain, processes in generators.items():
-            if isinstance(processes, Iterable) and not inspect.isgenerator(processes):
-                for process in processes:
-                    sim.add_sync_process(process, domain=domain)
-            else:
-                sim.add_sync_process(processes, domain=domain)
+    sim = Simulator(fragment)
+    for domain, period in clocks.items():
+        sim.add_clock(period / 1e9, domain=domain)
+    for domain, processes in generators.items():
+        def wrap(process):
+            def wrapper():
+                yield from process
+            return wrapper
+        if isinstance(processes, Iterable) and not inspect.isgenerator(processes):
+            for process in processes:
+                sim.add_sync_process(wrap(process), domain=domain)
+        else:
+            sim.add_sync_process(wrap(processes), domain=domain)
+
+    if vcd_name is not None:
+        with sim.write_vcd(vcd_name):
+            sim.run()
+    else:
         sim.run()