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back.{verilog,rtlil}: fix commit d83c4a1b.

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The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
This commit is contained in:
Catherine 2021-12-14 10:47:04 +00:00
parent a6a13dd612
commit 847e46927b
3 changed files with 3 additions and 3 deletions
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2
amaranth/back/rtlil.py
View file

@ -1034,6 +1034,6 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru
if ports is None:
warnings.warn("Implicit port determination is deprecated, specify ports explictly",
DeprecationWarning, stacklevel=2)
fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
return il_text

2
amaranth/back/verilog.py
View file

@ -47,6 +47,6 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru
if ports is None:
warnings.warn("Implicit port determination is deprecated, specify ports explictly",
DeprecationWarning, stacklevel=2)
fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
return verilog_text

2
tests/utils.py
View file

@ -71,7 +71,7 @@ class FHDLTestCase(unittest.TestCase):
mode=mode,
depth=depth,
script=script,
rtlil=rtlil.convert(Fragment.get(spec, platform="formal"), ports=())
rtlil=rtlil.convert_fragment(Fragment.get(spec, platform="formal").prepare())[0]
)
with subprocess.Popen(
[require_tool("sby"), "-f", "-d", spec_name],