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docs/stdlib/io: minor documentation clarity improvement.

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Catherine 2024-05-30 10:32:53 +00:00
parent 028d5d8073
commit 855545b6ff
1 changed files with 4 additions and 3 deletions
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7
amaranth/lib/io.py
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@ -726,10 +726,11 @@ class DDRBuffer(wiring.Component):
port : :class:`PortLike`
Port driven by the buffer.
i_domain : :class:`str`
Name of the input registers' clock domain. Only used when :py:`direction in (Input, Bidir)`.
Name of the input register's clock domain. Used when :py:`direction in (Input, Bidir)`.
Defaults to :py:`"sync"`.
o_domain : :class:`str`
Name of the output and output enable registers' clock domain. Only used when
:py:`direction in (Output, Bidir)`.
Name of the output and output enable registers' clock domain. Used when
:py:`direction in (Output, Bidir)`. Defaults to :py:`"sync"`.
Attributes
----------