hdl.dsl: warn if a case is defined after a default case.
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2 changed files with 26 additions and 0 deletions
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@ -497,6 +497,26 @@ class DSLTestCase(FHDLTestCase):
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with m.Case():
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pass
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def test_Case_after_Default_wrong(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Default():
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pass
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with self.assertWarnsRegex(SyntaxWarning,
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r"^A case defined after the default case will never be active$"):
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with m.Case():
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pass
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def test_Default_after_Default_wrong(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Default():
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pass
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with self.assertWarnsRegex(SyntaxWarning,
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r"^A case defined after the default case will never be active$"):
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with m.Default():
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pass
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def test_If_inside_Switch_wrong(self):
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m = Module()
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with m.Switch(self.s1):
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