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lib.cdc: avoid modifying synchronizers in their elaborate() method.

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This commit is contained in:
whitequark 2019-09-23 16:42:44 +00:00
parent 51f03bb509
commit 86f0f12b58
3 changed files with 34 additions and 22 deletions
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9
nmigen/vendor/xilinx_7series.py vendored
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@ -363,8 +363,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
def get_ff_sync(self, ff_sync):
m = Module()
for i, o in zip((ff_sync.i, *ff_sync._stages), ff_sync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
reset=ff_sync._reset, reset_less=ff_sync._reset_less,
attrs={"ASYNC_REG": "TRUE"})
for index in range(ff_sync._stages)]
for i, o in zip((ff_sync.i, *flops), flops):
m.d[ff_sync._o_domain] += o.eq(i)
m.d.comb += ff_sync.o.eq(ff_sync._stages[-1])
m.d.comb += ff_sync.o.eq(flops[-1])
return m

23
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -413,22 +413,27 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
def get_ff_sync(self, ff_sync):
m = Module()
for i, o in zip((ff_sync.i, *ff_sync._stages), ff_sync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
reset=ff_sync._reset, reset_less=ff_sync._reset_less,
attrs={"ASYNC_REG": "TRUE"})
for index in range(ff_sync._stages)]
for i, o in zip((ff_sync.i, *flops), flops):
m.d[ff_sync._o_domain] += o.eq(i)
m.d.comb += ff_sync.o.eq(multireg._stages[-1])
m.d.comb += ff_sync.o.eq(flops[-1])
return m
def get_reset_sync(self, resetsync):
def get_reset_sync(self, reset_sync):
m = Module()
m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
for i, o in zip((0, *resetsync._stages), resetsync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
flops = [Signal(1, name="stage{}".format(index), reset=1,
attrs={"ASYNC_REG": "TRUE"})
for index in range(reset_sync._stages)]
for i, o in zip((0, *flops), flops):
m.d.reset_sync += o.eq(i)
m.d.comb += [
ClockSignal("reset_sync").eq(ClockSignal(resetsync._domain)),
ResetSignal("reset_sync").eq(resetsync.arst),
ResetSignal(resetsync._domain).eq(resetsync._stages[-1])
ClockSignal("reset_sync").eq(ClockSignal(reset_sync._domain)),
ResetSignal("reset_sync").eq(reset_sync.arst),
ResetSignal(reset_sync._domain).eq(flops[-1])
]
return m