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build.plat,vendor._lattice: add Diamond escaping quirk.

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Partially addresses #546.
This commit is contained in:
Catherine 2024-05-30 11:10:00 +00:00
parent f0dd01eadf
commit 8da55299a5
2 changed files with 11 additions and 4 deletions
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11
amaranth/build/plat.py
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@ -330,8 +330,15 @@ class TemplatedPlatform(Platform):
return f"_{ord(match.group(1)[0]):02x}_"
return "".join(escape_one(m) for m in re.finditer(r"([^A-Za-z0-9_])|(.)", string))
def tcl_quote(string):
return '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"'
def tcl_quote(string, quirk=None):
escaped = '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"'
if quirk == "Diamond":
# Diamond seems to assign `clk\$2` as a name for the Verilog net `\clk$2 `, and
# `clk\\\$2` as a name for the Verilog net `\clk\$2 `.
return escaped.replace("\\", "\\\\")
else:
assert quirk is None
return escaped
def verbose(arg):
if get_override_flag("verbose"):

4
amaranth/vendor/_lattice.py
View file

@ -686,9 +686,9 @@ class LatticePlatform(TemplatedPlatform):
set_hierarchy_separator {/}
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote}}]
create_clock -name {{port_signal.name|tcl_quote("Diamond")}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote("Diamond")}}]
{% else -%}
create_clock -name {{net_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote}}]
create_clock -name {{net_signal.name|tcl_quote("Diamond")}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote("Diamond")}}]
{% endif %}
{% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}