fhdl.ir: record port direction explicitly.

No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.

nmigen/fhdl/ast.py

@@ -516,7 +516,7 @@ class Signal(Value, DUID):
 
         if name is None:
             try:
-                name = tracer.get_var_name()
+                name = tracer.get_var_name(depth=2 + src_loc_at)
             except tracer.NameNotFound:
                 name = "$signal"
         self.name = name
@@ -557,7 +557,8 @@ class Signal(Value, DUID):
         other : Value
             Object to base this Signal on.
         """
-        kw = dict(shape=cls.wrap(other).shape(), name=tracer.get_var_name())
+        kw = dict(shape=cls.wrap(other).shape(),
+                  name=tracer.get_var_name(depth=2 + src_loc_at))
         if isinstance(other, cls):
             kw.update(reset=other.reset, reset_less=other.reset_less, attrs=other.attrs)
         kw.update(kwargs)
@@ -749,9 +750,25 @@ class ValueDict(MutableMapping):
     def __iter__(self):
         return map(lambda x: None if x is None else x.value, sorted(self._inner))
 
+    def __eq__(self, other):
+        if not isinstance(other, ValueDict):
+            return False
+        if len(self) != len(other):
+            return False
+        for ak, bk in zip(self, other):
+            if ValueKey(ak) != ValueKey(bk):
+                return False
+            if self[ak] != other[bk]:
+                return False
+        return True
+
     def __len__(self):
         return len(self._inner)
 
+    def __repr__(self):
+        pairs = ["({!r}, {!r})".format(k, v) for k, v in self.items()]
+        return "ValueDict([{}])".format(", ".join(pairs))
+
 
 class ValueSet(MutableSet):
     def __init__(self, elements=()):

nmigen/fhdl/ir.py

@@ -14,17 +14,19 @@ class DomainError(Exception):
 
 class Fragment:
     def __init__(self):
-        self.ports = ValueSet()
+        self.ports = ValueDict()
         self.drivers = OrderedDict()
         self.statements = []
         self.domains = OrderedDict()
         self.subfragments = []
 
-    def add_ports(self, *ports):
-        self.ports.update(flatten(ports))
+    def add_ports(self, *ports, kind):
+        assert kind in ("i", "o", "io")
+        for port in flatten(ports):
+            self.ports[port] = kind
 
     def iter_ports(self):
-        yield from self.ports
+        yield from self.ports.keys()
 
     def drive(self, signal, domain=None):
         if domain not in self.drivers:
@@ -161,6 +163,7 @@ class Fragment:
             outs |= ports & sub_outs
 
         # We've computed the precise set of input and output ports.
-        self.add_ports(ins, outs)
+        self.add_ports(ins,  kind="i")
+        self.add_ports(outs, kind="o")
 
         return ins, outs