Fix several typos. NFC.

amaranth/_toolchain/cxx.py

@@ -12,7 +12,7 @@ def build_cxx(*, cxx_sources, output_name, include_dirs, macros):
 
     cwd = os.getcwd()
     try:
-        # Unforuntately, `ccompiler.compile` assumes the paths are relative, and interprets
+        # Unfortunately, `ccompiler.compile` assumes the paths are relative, and interprets
         # the directory name of the source path specially. That makes it necessary to build in
         # the output directory directly.
         os.chdir(build_dir.name)

amaranth/back/rtlil.py

@@ -1046,7 +1046,7 @@ def convert_fragment(fragment, name="top", *, emit_src=True):
 def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=True, **kwargs):
     # TODO(amaranth-0.4): remove
     if ports is None:
-        warnings.warn("Implicit port determination is deprecated, specify ports explictly",
+        warnings.warn("Implicit port determination is deprecated, specify ports explicitly",
                       DeprecationWarning, stacklevel=2)
     fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)

amaranth/back/verilog.py

@@ -45,7 +45,7 @@ def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
 def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=True, strip_internal_attrs=False, **kwargs):
     # TODO(amaranth-0.4): remove
     if ports is None:
-        warnings.warn("Implicit port determination is deprecated, specify ports explictly",
+        warnings.warn("Implicit port determination is deprecated, specify ports explicitly",
                       DeprecationWarning, stacklevel=2)
     fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)

amaranth/hdl/ast.py

@@ -854,7 +854,7 @@ class Cat(Value):
     Returns
     -------
     Value, inout
-        Resulting ``Value`` obtained by concatentation.
+        Resulting ``Value`` obtained by concatenation.
     """
     def __init__(self, *args, src_loc_at=0):
         super().__init__(src_loc_at=src_loc_at)

amaranth/lib/io.py

@@ -54,7 +54,7 @@ class Pin(Record):
     or tristate buffers that may include a 1:n gearbox. (A 1:2 gearbox is typically called "DDR".)
 
     A :class:`Pin` is identical to a :class:`Record` that uses the corresponding :meth:`pin_layout`
-    except that it allos accessing the parameters like ``width`` as attributes. It is legal to use
+    except that it allows accessing the parameters like ``width`` as attributes. It is legal to use
     a plain :class:`Record` anywhere a :class:`Pin` is used, provided that these attributes are
     not necessary.
 
@@ -83,7 +83,7 @@ class Pin(Record):
     i_clk:
         I/O buffer input clock. Synchronizes `i*`. Present if ``xdr`` is nonzero.
     i_fclk:
-        I/O buffer input fast clock. Synchronizes `i*` on higer gearbox ratios. Present if ``xdr``
+        I/O buffer input fast clock. Synchronizes `i*` on higher gearbox ratios. Present if ``xdr``
         is greater than 2.
     i : Signal, out
         I/O buffer input, without gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is

amaranth/vendor/xilinx.py

@@ -654,9 +654,9 @@ class XilinxPlatform(TemplatedPlatform):
         assert False
 
     def create_missing_domain(self, name):
-        # Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
+        # Xilinx devices have a global write enable (GWE) signal that asserted during configuration
         # and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
-        # syncronous to configuration clock, which is not used by most designs), even though it is
+        # synchronous to configuration clock, which is not used by most designs), even though it is
         # a low-skew global network, its deassertion may violate a setup/hold constraint with
         # relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
         # signal (if available). For details, see:

docs/changes.rst

@@ -64,7 +64,7 @@ Language changes
 * Added: :meth:`Value.shift_left` and :meth:`Value.shift_right`.
 * Added: :class:`ValueCastable`.
 * Deprecated: :class:`ast.UserValue`; use :class:`ValueCastable` instead.
-* Added: Divison and modulo operators can be used with a negative divisor.
+* Added: Division and modulo operators can be used with a negative divisor.
 
 
 Standard library changes