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vendor.xilinx: avoid using / for hierarchy in ISE constraint files.

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H-S-S-11 2021-09-25 11:41:23 +01:00 committed by GitHub
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nmigen/vendor/xilinx.py
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@ -276,7 +276,7 @@ class XilinxPlatform(TemplatedPlatform):
{% endfor %} {% endfor %}
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%} {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
NET "{{net_signal|hierarchy("/")}}" TNM_NET="PRD{{net_signal|hierarchy("/")}}"; NET "{{net_signal|hierarchy("/")}}" TNM_NET="PRD{{net_signal|hierarchy("/")}}";
TIMESPEC "TS{{net_signal|hierarchy("/")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%; TIMESPEC "TS{{net_signal|hierarchy("__")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
{% endfor %} {% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}} {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""" """