Clean up imports.

This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.

nmigen/__init__.py

@@ -2,13 +2,5 @@ from ._version import get_versions
 __version__ = get_versions()['version']
 del get_versions
 
-from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
+from .hdl import *
-from .hdl.dsl import Module
+from .lib import *
-from .hdl.cd import ClockDomain
-from .hdl.ir import Elaboratable, Fragment, Instance
-from .hdl.mem import Memory
-from .hdl.rec import Record
-from .hdl.xfrm import ResetInserter, CEInserter
-
-from .lib.cdc import MultiReg
-# from .lib.io import

nmigen/formal.py

@@ -1 +1,2 @@
 from .hdl.ast import AnyConst, AnySeq, Assert, Assume
+from .hdl.ast import Past, Stable, Rose, Fell

nmigen/hdl/__init__.py

@@ -0,0 +1,7 @@
+from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
+from .dsl import Module
+from .cd import ClockDomain
+from .ir import Elaboratable, Fragment, Instance
+from .mem import Memory
+from .rec import Record
+from .xfrm import DomainRenamer, ResetInserter, CEInserter

nmigen/lib/__init__.py

@@ -0,0 +1 @@
+from .cdc import MultiReg

nmigen/test/test_lib_cdc.py

@@ -1,7 +1,5 @@
 from .tools import *
-from ..hdl.ast import *
+from ..hdl import *
-from ..hdl.cd import *
-from ..hdl.dsl import *
 from ..back.pysim import *
 from ..lib.cdc import *
 

nmigen/test/test_lib_coding.py

@@ -1,7 +1,6 @@
 from .tools import *
-from ..hdl.ast import *
+from ..hdl import *
-from ..hdl.dsl import *
+from ..formal import *
-from ..hdl.ir import *
 from ..back.pysim import *
 from ..lib.coding import *
 

nmigen/test/test_lib_fifo.py

@@ -1,10 +1,6 @@
 from .tools import *
-from ..hdl.ast import *
+from ..hdl import *
-from ..hdl.dsl import *
+from ..formal import *
-from ..hdl.mem import *
-from ..hdl.ir import *
-from ..hdl.xfrm import *
-from ..hdl.cd import *
 from ..back.pysim import *
 from ..lib.fifo import *
 

nmigen/test/test_lib_io.py

@@ -1,6 +1,7 @@
 from .tools import *
-from ..hdl.ast import *
+from ..hdl import *
 from ..hdl.rec import *
+from ..back.pysim import *
 from ..lib.io import *
 
 

nmigen/vendor/fpga/lattice_ice40.py

@@ -3,9 +3,7 @@ import os
 import subprocess
 import tempfile
 
-from ...hdl.ast import *
+from ...hdl import *
-from ...hdl.dsl import *
-from ...hdl.ir import *
 from ...build import *