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back.rtlil: do not translate empty fragments.

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The resulting Verilog confuses some frontends.
This commit is contained in:
whitequark 2018-12-23 09:20:02 +00:00
parent 45a474788c
commit 9faa1d3742
1 changed files with 3 additions and 0 deletions
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3
nmigen/back/rtlil.py
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@ -627,6 +627,9 @@ def convert_fragment(builder, fragment, name, top):
# name) names. # name) names.
memories = OrderedDict() memories = OrderedDict()
for subfragment, sub_name in fragment.subfragments: for subfragment, sub_name in fragment.subfragments:
if not subfragment.ports:
continue
sub_params = OrderedDict() sub_params = OrderedDict()
if hasattr(subfragment, "parameters"): if hasattr(subfragment, "parameters"):
for param_name, param_value in subfragment.parameters.items(): for param_name, param_value in subfragment.parameters.items():