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back.pysim: if requested, write a gtkw file with a useful preset.

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This commit is contained in:
whitequark 2018-12-14 08:04:29 +00:00
parent cb998d891b
commit a10791e160
2 changed files with 43 additions and 3 deletions
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5
examples/ctrl.py
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@ -21,7 +21,10 @@ frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
sim = pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o])
sim.add_clock("sync", 1e-6)
def ce_proc():
yield; yield; yield