hdl.ast: handle a common typo, such as Signal(1, True).

This commit is contained in:
whitequark 2019-04-03 14:59:01 +00:00
parent c9c9307a5e
commit a74cacdc69
2 changed files with 8 additions and 0 deletions

View file

@ -581,6 +581,8 @@ class Signal(Value, DUID):
attrs=None, decoder=None, src_loc_at=0):
super().__init__(src_loc_at=src_loc_at)
if name is not None and not isinstance(name, str):
raise TypeError("Name must be a string, not '{!r}'".format(name))
self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal")
if shape is None:

View file

@ -429,6 +429,12 @@ class SignalTestCase(FHDLTestCase):
s2 = Signal(name="sig")
self.assertEqual(s2.name, "sig")
def test_name_bad(self):
with self.assertRaises(TypeError,
msg="Name must be a string, not 'True'"):
# A common typo: forgetting to put parens around width and signedness
Signal(1, True)
def test_reset(self):
s1 = Signal(4, reset=0b111, reset_less=True)
self.assertEqual(s1.reset, 0b111)