hdl.ast: handle a common typo, such as Signal(1, True).
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@ -581,6 +581,8 @@ class Signal(Value, DUID):
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attrs=None, decoder=None, src_loc_at=0):
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super().__init__(src_loc_at=src_loc_at)
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if name is not None and not isinstance(name, str):
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raise TypeError("Name must be a string, not '{!r}'".format(name))
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self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal")
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if shape is None:
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@ -429,6 +429,12 @@ class SignalTestCase(FHDLTestCase):
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s2 = Signal(name="sig")
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self.assertEqual(s2.name, "sig")
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def test_name_bad(self):
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with self.assertRaises(TypeError,
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msg="Name must be a string, not 'True'"):
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# A common typo: forgetting to put parens around width and signedness
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Signal(1, True)
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def test_reset(self):
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s1 = Signal(4, reset=0b111, reset_less=True)
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self.assertEqual(s1.reset, 0b111)
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