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build.dsl: replace extras= with Attrs().

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This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
This commit is contained in:
whitequark 2019-06-05 07:02:08 +00:00
parent c52cd72d3e
commit ab3f103e5a
7 changed files with 262 additions and 253 deletions
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85
nmigen/test/test_build_dsl.py
View file

@ -23,7 +23,7 @@ class PinsTestCase(FHDLTestCase):
"pmod_0:1": "A1",
"pmod_0:2": "A2",
}
self.assertEqual(list(p.map_names(mapping, p)), ["A0", "A1", "A2"])
self.assertEqual(p.map_names(mapping, p), ["A0", "A1", "A2"])
def test_map_names_recur(self):
p = Pins("0", conn=("pmod", 0))
@ -31,7 +31,7 @@ class PinsTestCase(FHDLTestCase):
"pmod_0:0": "ext_0:1",
"ext_0:1": "A1",
}
self.assertEqual(list(p.map_names(mapping, p)), ["A1"])
self.assertEqual(p.map_names(mapping, p), ["A1"])
def test_wrong_names(self):
with self.assertRaises(TypeError,
@ -51,7 +51,7 @@ class PinsTestCase(FHDLTestCase):
with self.assertRaises(NameError,
msg="Resource (pins io pmod_0:0 pmod_0:1 pmod_0:2) refers to nonexistent "
"connector pin pmod_0:1"):
list(p.map_names(mapping, p))
p.map_names(mapping, p)
class DiffPairsTestCase(FHDLTestCase):
@ -84,81 +84,90 @@ class DiffPairsTestCase(FHDLTestCase):
dp = DiffPairs("A0", "B0 B1")
class AttrsTestCase(FHDLTestCase):
def test_basic(self):
a = Attrs(IO_STANDARD="LVCMOS33", PULLUP="1")
self.assertEqual(a["IO_STANDARD"], "LVCMOS33")
self.assertEqual(repr(a), "(attrs IO_STANDARD=LVCMOS33 PULLUP=1)")
def test_wrong_value(self):
with self.assertRaises(TypeError,
msg="Attribute value must be a string, not 1"):
a = Attrs(FOO=1)
class SubsignalTestCase(FHDLTestCase):
def test_basic_pins(self):
s = Subsignal("a", Pins("A0"), extras={"IOSTANDARD": "LVCMOS33"})
self.assertEqual(repr(s), "(subsignal a (pins io A0) IOSTANDARD=LVCMOS33)")
s = Subsignal("a", Pins("A0"), Attrs(IOSTANDARD="LVCMOS33"))
self.assertEqual(repr(s),
"(subsignal a (pins io A0) (attrs IOSTANDARD=LVCMOS33))")
def test_basic_diffpairs(self):
s = Subsignal("a", DiffPairs("A0", "B0"))
self.assertEqual(repr(s), "(subsignal a (diffpairs io (p A0) (n B0)) )")
self.assertEqual(repr(s),
"(subsignal a (diffpairs io (p A0) (n B0)) (attrs ))")
def test_basic_subsignals(self):
s = Subsignal("a",
Subsignal("b", Pins("A0")),
Subsignal("c", Pins("A1")))
self.assertEqual(repr(s),
"(subsignal a (subsignal b (pins io A0) ) (subsignal c (pins io A1) ) )")
"(subsignal a (subsignal b (pins io A0) (attrs )) "
"(subsignal c (pins io A1) (attrs )) (attrs ))")
def test_extras(self):
def test_attrs(self):
s = Subsignal("a",
Subsignal("b", Pins("A0")),
Subsignal("c", Pins("A0"), extras={"SLEW": "FAST"}),
extras={"IOSTANDARD": "LVCMOS33"})
self.assertEqual(s.extras, {"IOSTANDARD": "LVCMOS33"})
self.assertEqual(s.io[0].extras, {"IOSTANDARD": "LVCMOS33"})
self.assertEqual(s.io[1].extras, {"SLEW": "FAST", "IOSTANDARD": "LVCMOS33"})
Subsignal("c", Pins("A0"), Attrs(SLEW="FAST")),
Attrs(IOSTANDARD="LVCMOS33"))
self.assertEqual(s.attrs, {"IOSTANDARD": "LVCMOS33"})
self.assertEqual(s.ios[0].attrs, {})
self.assertEqual(s.ios[1].attrs, {"SLEW": "FAST"})
def test_empty_io(self):
with self.assertRaises(TypeError, msg="Missing I/O constraints"):
def test_attrs_many(self):
s = Subsignal("a", Pins("A0"), Attrs(SLEW="FAST"), Attrs(PULLUP="1"))
self.assertEqual(s.attrs, {"SLEW": "FAST", "PULLUP": "1"})
def test_wrong_empty_io(self):
with self.assertRaises(ValueError, msg="Missing I/O constraints"):
s = Subsignal("a")
def test_wrong_io(self):
with self.assertRaises(TypeError,
msg="I/O constraint must be one of Pins, DiffPairs or Subsignal, not 'wrong'"):
msg="I/O constraint must be one of Pins, DiffPairs, Subsignal, or Attrs, "
"not 'wrong'"):
s = Subsignal("a", "wrong")
def test_wrong_pins(self):
with self.assertRaises(TypeError,
msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
"(pins io A0) is followed by (pins io A1)"):
msg="Pins and DiffPairs are incompatible with other location or subsignal "
"constraints, but (pins io A1) appears after (pins io A0)"):
s = Subsignal("a", Pins("A0"), Pins("A1"))
def test_wrong_diffpairs(self):
with self.assertRaises(TypeError,
msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
"(diffpairs io (p A0) (n B0)) is followed by "
"(pins io A1)"):
msg="Pins and DiffPairs are incompatible with other location or subsignal "
"constraints, but (pins io A1) appears after (diffpairs io (p A0) (n B0))"):
s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
def test_wrong_subsignals(self):
with self.assertRaises(TypeError,
msg="A Subsignal can only be followed by more Subsignals, but "
"(subsignal b (pins io A0) ) is followed by (pins io B0)"):
msg="Pins and DiffPairs are incompatible with other location or subsignal "
"constraints, but (pins io B0) appears after (subsignal b (pins io A0) "
"(attrs ))"):
s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
def test_wrong_extras(self):
with self.assertRaises(TypeError,
msg="Extra constraints must be a dict, not [(pins io B0)]"):
s = Subsignal("a", Pins("A0"), extras=[Pins("B0")])
with self.assertRaises(TypeError,
msg="Extra constraint key must be a string, not 1"):
s = Subsignal("a", Pins("A0"), extras={1: 2})
with self.assertRaises(TypeError,
msg="Extra constraint value must be a string, not 2"):
s = Subsignal("a", Pins("A0"), extras={"1": 2})
class ResourceTestCase(FHDLTestCase):
def test_basic(self):
r = Resource("serial", 0,
Subsignal("tx", Pins("A0", dir="o")),
Subsignal("rx", Pins("A1", dir="i")),
extras={"IOSTANDARD": "LVCMOS33"})
Attrs(IOSTANDARD="LVCMOS33"))
self.assertEqual(repr(r), "(resource serial 0"
" (subsignal tx (pins o A0) IOSTANDARD=LVCMOS33)"
" (subsignal rx (pins i A1) IOSTANDARD=LVCMOS33)"
" IOSTANDARD=LVCMOS33)")
" (subsignal tx (pins o A0) (attrs ))"
" (subsignal rx (pins i A1) (attrs ))"
" (attrs IOSTANDARD=LVCMOS33))")
class ConnectorTestCase(FHDLTestCase):

24
nmigen/test/test_build_res.py
View file

@ -6,7 +6,7 @@ from ..build.res import *
from .tools import *
class ConstraintManagerTestCase(FHDLTestCase):
class ResourceManagerTestCase(FHDLTestCase):
def setUp(self):
self.resources = [
Resource("clk100", 0, DiffPairs("H1", "H2", dir="i")),
@ -20,14 +20,14 @@ class ConstraintManagerTestCase(FHDLTestCase):
self.connectors = [
Connector("pmod", 0, "B0 B1 B2 B3 - -"),
]
self.cm = ConstraintManager(self.resources, self.connectors, [])
self.cm = ResourceManager(self.resources, self.connectors, [])
def test_basic(self):
self.clocks = [
("clk100", 100),
(("clk50", 0), 50),
]
self.cm = ConstraintManager(self.resources, self.connectors, self.clocks)
self.cm = ResourceManager(self.resources, self.connectors, self.clocks)
self.assertEqual(self.cm.resources, {
("clk100", 0): self.resources[0],
("clk50", 0): self.resources[1],
@ -177,8 +177,8 @@ class ConstraintManagerTestCase(FHDLTestCase):
def test_wrong_resources_duplicate(self):
with self.assertRaises(NameError,
msg="Trying to add (resource user_led 0 (pins o A1) ), but "
"(resource user_led 0 (pins o A0) ) has the same name and number"):
msg="Trying to add (resource user_led 0 (pins o A1) (attrs )), but "
"(resource user_led 0 (pins o A0) (attrs )) has the same name and number"):
self.cm.add_resources([Resource("user_led", 0, Pins("A1", dir="o"))])
def test_wrong_connectors(self):
@ -192,7 +192,7 @@ class ConstraintManagerTestCase(FHDLTestCase):
self.cm.add_connectors([Connector("pmod", 0, "1 2")])
def test_wrong_lookup(self):
with self.assertRaises(ConstraintError,
with self.assertRaises(ResourceError,
msg="Resource user_led#1 does not exist"):
r = self.cm.lookup("user_led", 1)
@ -203,7 +203,7 @@ class ConstraintManagerTestCase(FHDLTestCase):
self.cm.add_clock("i2c", 0, 10e6)
def test_wrong_frequency_tristate(self):
with self.assertRaises(ConstraintError,
with self.assertRaises(ResourceError,
msg="Cannot constrain frequency of resource clk50#0 because "
"it has been requested as a tristate buffer"):
self.cm.add_clock("clk50", 0, 20e6)
@ -211,13 +211,13 @@ class ConstraintManagerTestCase(FHDLTestCase):
list(self.cm.iter_clock_constraints())
def test_wrong_frequency_duplicate(self):
with self.assertRaises(ConstraintError,
with self.assertRaises(ResourceError,
msg="Resource clk100#0 is already constrained to a frequency of 10.000000 MHz"):
self.cm.add_clock("clk100", 0, 10e6)
self.cm.add_clock("clk100", 0, 5e6)
def test_wrong_request_duplicate(self):
with self.assertRaises(ConstraintError,
with self.assertRaises(ResourceError,
msg="Resource user_led#0 has already been requested"):
self.cm.request("user_led", 0)
self.cm.request("user_led", 0)
@ -238,7 +238,8 @@ class ConstraintManagerTestCase(FHDLTestCase):
def test_wrong_request_with_dir_dict(self):
with self.assertRaises(TypeError,
msg="Directions must be a dict, not 'i', because (resource i2c 0 (subsignal scl "
"(pins o N10) ) (subsignal sda (pins io N11) ) ) has subsignals"):
"(pins o N10) (attrs )) (subsignal sda (pins io N11) (attrs )) (attrs )) "
"has subsignals"):
i2c = self.cm.request("i2c", 0, dir="i")
def test_wrong_request_with_wrong_xdr(self):
@ -249,5 +250,6 @@ class ConstraintManagerTestCase(FHDLTestCase):
def test_wrong_request_with_xdr_dict(self):
with self.assertRaises(TypeError,
msg="Data rate must be a dict, not 2, because (resource i2c 0 (subsignal scl "
"(pins o N10) ) (subsignal sda (pins io N11) ) ) has subsignals"):
"(pins o N10) (attrs )) (subsignal sda (pins io N11) (attrs )) (attrs )) "
"has subsignals"):
i2c = self.cm.request("i2c", 0, xdr=2)