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sim.pysim: admit non-signals in write_vcd(traces=...).

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Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
This commit is contained in:
Catherine 2023-11-28 12:14:08 +00:00
parent c6000b1097
commit b0b193f1ad
1 changed files with 4 additions and 3 deletions
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7
amaranth/sim/pysim.py
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@ -64,9 +64,10 @@ class _VCDWriter:
trace_names = SignalDict()
for trace in traces:
if trace not in signal_names:
trace_names[trace] = {("bench", trace.name)}
self.traces.append(trace)
for trace_signal in trace._rhs_signals():
if trace_signal not in signal_names:
trace_names[trace_signal] = {("bench", trace_signal.name)}
self.traces.append(trace_signal)
if self.vcd_writer is None:
return