hdl.MemoryInstance: refactor and add first-class simulation support.
This commit is contained in:
Wanda
Catherine
parent
f4daf74634
commit
b6c5294e50
9 changed files with 525 additions and 201 deletions
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@ -787,69 +787,71 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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return f"\\{fragment.type}", port_map, params
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if isinstance(fragment, _mem.MemoryInstance):
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memory = fragment.memory
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init = "".join(format(_ast.Const(elem, _ast.unsigned(memory.width)).value, f"0{memory.width}b") for elem in reversed(memory.init))
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init = _ast.Const(int(init or "0", 2), memory.depth * memory.width)
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init = "".join(format(_ast.Const(elem, _ast.unsigned(fragment._width)).value, f"0{fragment._width}b") for elem in reversed(fragment._init))
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init = _ast.Const(int(init or "0", 2), fragment._depth * fragment._width)
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rd_clk = []
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rd_clk_enable = 0
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rd_clk_polarity = 0
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rd_transparency_mask = 0
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for index, port in enumerate(fragment.read_ports):
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if port.domain != "comb":
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cd = fragment.domains[port.domain]
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for index, port in enumerate(fragment._read_ports):
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if port._domain is not None:
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cd = fragment.domains[port._domain]
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rd_clk.append(cd.clk)
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if cd.clk_edge == "pos":
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rd_clk_polarity |= 1 << index
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rd_clk_enable |= 1 << index
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if port.transparent:
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for write_index, write_port in enumerate(fragment.write_ports):
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if port.domain == write_port.domain:
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rd_transparency_mask |= 1 << (index * len(fragment.write_ports) + write_index)
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for write_index in port._transparency:
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rd_transparency_mask |= 1 << (index * len(fragment._write_ports) + write_index)
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else:
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rd_clk.append(_ast.Const(0, 1))
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wr_clk = []
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wr_clk_enable = 0
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wr_clk_polarity = 0
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for index, port in enumerate(fragment.write_ports):
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cd = fragment.domains[port.domain]
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for index, port in enumerate(fragment._write_ports):
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cd = fragment.domains[port._domain]
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wr_clk.append(cd.clk)
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wr_clk_enable |= 1 << index
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if cd.clk_edge == "pos":
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wr_clk_polarity |= 1 << index
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params = {
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"MEMID": builder._make_name(hierarchy[-1], local=False),
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"SIZE": memory.depth,
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"SIZE": fragment._depth,
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"OFFSET": 0,
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"ABITS": _ast.Shape.cast(range(memory.depth)).width,
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"WIDTH": memory.width,
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"ABITS": _ast.Shape.cast(range(fragment._depth)).width,
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"WIDTH": fragment._width,
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"INIT": init,
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"RD_PORTS": len(fragment.read_ports),
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"RD_CLK_ENABLE": _ast.Const(rd_clk_enable, max(1, len(fragment.read_ports))),
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"RD_CLK_POLARITY": _ast.Const(rd_clk_polarity, max(1, len(fragment.read_ports))),
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"RD_TRANSPARENCY_MASK": _ast.Const(rd_transparency_mask, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_COLLISION_X_MASK": _ast.Const(0, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
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"RD_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_CE_OVER_SRST": _ast.Const(0, max(1, len(fragment.read_ports))),
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"RD_ARST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_SRST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"RD_INIT_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
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"WR_PORTS": len(fragment.write_ports),
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"WR_CLK_ENABLE": _ast.Const(wr_clk_enable, max(1, len(fragment.write_ports))),
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"WR_CLK_POLARITY": _ast.Const(wr_clk_polarity, max(1, len(fragment.write_ports))),
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"WR_PRIORITY_MASK": _ast.Const(0, max(1, len(fragment.write_ports) * len(fragment.write_ports))),
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"WR_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.write_ports))),
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"RD_PORTS": len(fragment._read_ports),
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"RD_CLK_ENABLE": _ast.Const(rd_clk_enable, max(1, len(fragment._read_ports))),
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"RD_CLK_POLARITY": _ast.Const(rd_clk_polarity, max(1, len(fragment._read_ports))),
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"RD_TRANSPARENCY_MASK": _ast.Const(rd_transparency_mask, max(1, len(fragment._read_ports) * len(fragment._write_ports))),
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"RD_COLLISION_X_MASK": _ast.Const(0, max(1, len(fragment._read_ports) * len(fragment._write_ports))),
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"RD_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment._read_ports))),
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"RD_CE_OVER_SRST": _ast.Const(0, max(1, len(fragment._read_ports))),
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"RD_ARST_VALUE": _ast.Const(0, len(fragment._read_ports) * fragment._width),
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"RD_SRST_VALUE": _ast.Const(0, len(fragment._read_ports) * fragment._width),
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"RD_INIT_VALUE": _ast.Const(0, len(fragment._read_ports) * fragment._width),
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"WR_PORTS": len(fragment._write_ports),
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"WR_CLK_ENABLE": _ast.Const(wr_clk_enable, max(1, len(fragment._write_ports))),
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"WR_CLK_POLARITY": _ast.Const(wr_clk_polarity, max(1, len(fragment._write_ports))),
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"WR_PRIORITY_MASK": _ast.Const(0, max(1, len(fragment._write_ports) * len(fragment._write_ports))),
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"WR_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment._write_ports))),
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}
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def make_en(port):
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if len(port._data) == 0:
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return _ast.Const(0, 0)
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granularity = len(port._data) // len(port._en)
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return _ast.Cat(en_bit.replicate(granularity) for en_bit in port._en)
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port_map = {
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"\\RD_CLK": _ast.Cat(rd_clk),
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"\\RD_EN": _ast.Cat(port.en for port in fragment.read_ports),
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"\\RD_ARST": _ast.Const(0, len(fragment.read_ports)),
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"\\RD_SRST": _ast.Const(0, len(fragment.read_ports)),
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"\\RD_ADDR": _ast.Cat(port.addr for port in fragment.read_ports),
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"\\RD_DATA": _ast.Cat(port.data for port in fragment.read_ports),
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"\\RD_EN": _ast.Cat(port._en for port in fragment._read_ports),
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"\\RD_ARST": _ast.Const(0, len(fragment._read_ports)),
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"\\RD_SRST": _ast.Const(0, len(fragment._read_ports)),
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"\\RD_ADDR": _ast.Cat(port._addr for port in fragment._read_ports),
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"\\RD_DATA": _ast.Cat(port._data for port in fragment._read_ports),
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"\\WR_CLK": _ast.Cat(wr_clk),
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"\\WR_EN": _ast.Cat(_ast.Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in fragment.write_ports),
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"\\WR_ADDR": _ast.Cat(port.addr for port in fragment.write_ports),
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"\\WR_DATA": _ast.Cat(port.data for port in fragment.write_ports),
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"\\WR_EN": _ast.Cat(make_en(port) for port in fragment._write_ports),
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"\\WR_ADDR": _ast.Cat(port._addr for port in fragment._write_ports),
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"\\WR_DATA": _ast.Cat(port._data for port in fragment._write_ports),
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}
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return "$mem_v2", port_map, params
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@ -913,7 +915,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
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if isinstance(subfragment, _ir.Instance):
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src = _src(subfragment.src_loc)
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elif isinstance(subfragment, _mem.MemoryInstance):
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src = _src(subfragment.memory.src_loc)
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src = _src(subfragment._src_loc)
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else:
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src = ""
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