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genlib.cdc.MultiReg: pull in from Migen.

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whitequark 2018-12-12 10:12:35 +00:00
parent 263d577323
commit bc60631d68
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examples/cdc.py Normal file
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from nmigen.fhdl import *
from nmigen.back import rtlil, verilog
from nmigen.genlib.cdc import *
sys = ClockDomain()
i, o = Signal(name="i"), Signal(name="o")
frag = MultiReg(i, o).get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[i, o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[i, o], clock_domains={"sys": sys}))