hdl.ir: accept LHS signals like slices as Instance io ports.

This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)

nmigen/test/test_hdl_ir.py

@@ -603,7 +603,7 @@ class InstanceTestCase(FHDLTestCase):
             i_rst=self.rst,
             o_stb=self.stb,
             o_data=Cat(self.datal, self.datah),
-            io_pins=self.pins
+            io_pins=self.pins[:]
         )
         self.wrap = Fragment()
         self.wrap.add_subfragment(self.inst)