usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather than BUFGCE.

Browse source 
Fixes #438 (again).
This commit is contained in:
whitequark 2020-07-31 14:45:38 +00:00
parent 07dc163105
commit c9662c5ff8
2 changed files with 12 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
nmigen/vendor/xilinx_7series.py vendored
View file

@ -168,10 +168,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
ready = Signal() ready = Signal()
m.submodules += Instance("STARTUPE2", o_EOS=ready) m.submodules += Instance("STARTUPE2", o_EOS=ready)
m.domains += ClockDomain("sync", reset_less=self.default_rst is None) m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
m.submodules += Instance("BUFGCE", # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
p_SIM_DEVICE="7SERIES", # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
i_CE=ready, # breaks Vivado 2017.4.
i_I=clk_i, m.submodules += Instance("BUFGCTRL",
i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1),
i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
o_O=ClockSignal("sync") o_O=ClockSignal("sync")
) )
if self.default_rst is not None: if self.default_rst is not None:

10
nmigen/vendor/xilinx_ultrascale.py vendored
View file

@ -168,10 +168,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
ready = Signal() ready = Signal()
m.submodules += Instance("STARTUPE3", o_EOS=ready) m.submodules += Instance("STARTUPE3", o_EOS=ready)
m.domains += ClockDomain("sync", reset_less=self.default_rst is None) m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
m.submodules += Instance("BUFGCE", # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
p_SIM_DEVICE="ULTRASCALE", # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
i_CE=ready, # breaks Vivado 2017.4.
i_I=clk_i, m.submodules += Instance("BUFGCTRL",
i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1),
i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
o_O=ClockSignal("sync") o_O=ClockSignal("sync")
) )
if self.default_rst is not None: if self.default_rst is not None: