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back.rtlil: don't cache wires for legalized switch tests.

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This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
This commit is contained in:
whitequark 2019-10-02 07:51:49 +00:00
parent d3f7cc8ed2
commit d139f340b3
1 changed files with 11 additions and 3 deletions
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14
nmigen/back/rtlil.py
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@ -681,9 +681,17 @@ class _StatementCompiler(xfrm.StatementVisitor):
def on_Switch(self, stmt): def on_Switch(self, stmt):
self._check_rhs(stmt.test) self._check_rhs(stmt.test)
if stmt not in self._test_cache: if not self.state.expansions:
self._test_cache[stmt] = self.rhs_compiler(stmt.test) # We repeatedly translate the same switches over and over (see the LHSGroupAnalyzer
test_sigspec = self._test_cache[stmt] # related code below), and translating the switch test only once helps readability.
if stmt not in self._test_cache:
self._test_cache[stmt] = self.rhs_compiler(stmt.test)
test_sigspec = self._test_cache[stmt]
else:
# However, if the switch test contains an illegal value, then it may not be cached
# (since the illegal value will be repeatedly replaced with different constants), so
# don't cache anything in that case.
test_sigspec = self.rhs_compiler(stmt.test)
with self._case.switch(test_sigspec, src=src(stmt.src_loc)) as switch: with self._case.switch(test_sigspec, src=src(stmt.src_loc)) as switch:
for values, stmts in stmt.cases.items(): for values, stmts in stmt.cases.items():