back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.

2019-10-02 03:50:20 +00:00 · 2019-10-02 03:50:20 +00:00 · d3f7cc8ed2
parent 3a1dae591b
commit d3f7cc8ed2
1 changed files with 1 additions and 1 deletions
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@ -485,7 +485,7 @@ class _RHSValueCompiler(_ValueCompiler):
        lhs, rhs = value.operands
        lhs_bits, lhs_sign = lhs.shape()
        rhs_bits, rhs_sign = rhs.shape()
-        if lhs_sign == rhs_sign:
+        if lhs_sign == rhs_sign or value.op in ("<<", ">>", "**"):
            lhs_wire = self(lhs)
            rhs_wire = self(rhs)
        else: