sim: remove dead code. NFC
This is a remnant of feature added in commit11f7b887
and removed in commit994fa815
.
This commit is contained in:
parent
f49074f439
commit
d1895108c3
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@ -23,7 +23,7 @@ class _VCDWriter:
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def decode_to_vcd(format, value):
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def decode_to_vcd(format, value):
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return format.format(value).expandtabs().replace(" ", "_")
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return format.format(value).expandtabs().replace(" ", "_")
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def __init__(self, state, design, *, vcd_file, gtkw_file=None, traces=(), fs_per_delta=0, processes=()):
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def __init__(self, state, design, *, vcd_file, gtkw_file=None, traces=(), fs_per_delta=0):
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self.state = state
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self.state = state
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self.fs_per_delta = fs_per_delta
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self.fs_per_delta = fs_per_delta
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@ -236,26 +236,6 @@ class _VCDWriter:
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vcd_vars.append(row_vcd_vars)
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vcd_vars.append(row_vcd_vars)
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gtkw_names.append(row_gtkw_names)
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gtkw_names.append(row_gtkw_names)
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self.vcd_process_vars = {}
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if fs_per_delta == 0:
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return # Not useful without delta cycle expansion.
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for index, process in enumerate(processes):
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func_name = process.constructor.__name__
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func_file = os.path.basename(process.constructor.__code__.co_filename)
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func_line = process.constructor.__code__.co_firstlineno
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for name in (
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f"{process.constructor.__name__}",
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f"{process.constructor.__name__}!{func_file};{func_line}",
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f"{process.constructor.__name__}#{index}",
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):
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try:
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self.vcd_process_vars[process] = self.vcd_writer.register_var(
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scope=("debug", "proc"), name=name, var_type="string", size=None,
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init="(init)")
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break
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except KeyError:
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pass # try another name
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def update_signal(self, timestamp, signal):
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def update_signal(self, timestamp, signal):
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for (vcd_var, repr) in self.vcd_signal_vars.get(signal, ()):
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for (vcd_var, repr) in self.vcd_signal_vars.get(signal, ()):
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if isinstance(repr, Value):
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if isinstance(repr, Value):
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@ -723,8 +703,7 @@ class PySimEngine(BaseEngine):
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@contextmanager
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@contextmanager
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def write_vcd(self, *, vcd_file, gtkw_file, traces, fs_per_delta):
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def write_vcd(self, *, vcd_file, gtkw_file, traces, fs_per_delta):
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vcd_writer = _VCDWriter(self._state, self._design,
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vcd_writer = _VCDWriter(self._state, self._design,
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vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces, fs_per_delta=fs_per_delta,
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vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces, fs_per_delta=fs_per_delta)
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processes=self._testbenches)
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try:
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try:
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self._vcd_writers.append(vcd_writer)
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self._vcd_writers.append(vcd_writer)
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yield
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yield
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