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hdl.ast: deprecate Repl and remove from AST; add Value.replicate.

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Charlotte 2023-06-22 11:30:54 +10:00 • committed by Catherine
parent b1cce87630
commit d218273b9b
13 changed files with 83 additions and 95 deletions
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39
tests/test_hdl_ast.py
View file

@ -353,6 +353,23 @@ class ValueTestCase(FHDLTestCase):
r"^Rotate amount must be an integer, not 'str'$"):
Const(31).rotate_right("str")
def test_replicate_shape(self):
s1 = Const(10).replicate(3)
self.assertEqual(s1.shape(), unsigned(12))
self.assertIsInstance(s1.shape(), Shape)
s2 = Const(10).replicate(0)
self.assertEqual(s2.shape(), unsigned(0))
def test_replicate_count_wrong(self):
with self.assertRaises(TypeError):
Const(10).replicate(-1)
with self.assertRaises(TypeError):
Const(10).replicate("str")
def test_replicate_repr(self):
s = Const(10).replicate(3)
self.assertEqual(repr(s), "(cat (const 4'd10) (const 4'd10) (const 4'd10))")
class ConstTestCase(FHDLTestCase):
def test_shape(self):
@ -863,33 +880,19 @@ class CatTestCase(FHDLTestCase):
class ReplTestCase(FHDLTestCase):
def test_shape(self):
s1 = Repl(Const(10), 3)
self.assertEqual(s1.shape(), unsigned(12))
self.assertIsInstance(s1.shape(), Shape)
s2 = Repl(Const(10), 0)
self.assertEqual(s2.shape(), unsigned(0))
def test_count_wrong(self):
with self.assertRaises(TypeError):
Repl(Const(10), -1)
with self.assertRaises(TypeError):
Repl(Const(10), "str")
def test_repr(self):
s = Repl(Const(10), 3)
self.assertEqual(repr(s), "(repl (const 4'd10) 3)")
@_ignore_deprecated
def test_cast(self):
r = Repl(0, 3)
self.assertEqual(repr(r), "(repl (const 1'd0) 3)")
self.assertEqual(repr(r), "(cat (const 1'd0) (const 1'd0) (const 1'd0))")
@_ignore_deprecated
def test_int_01(self):
with warnings.catch_warnings():
warnings.filterwarnings(action="error", category=SyntaxWarning)
Repl(0, 3)
Repl(1, 3)
@_ignore_deprecated
def test_int_wrong(self):
with self.assertWarnsRegex(SyntaxWarning,
r"^Value argument of Repl\(\) is a bare integer 2 used in bit vector context; "

17
tests/test_hdl_xfrm.py
View file

@ -556,7 +556,22 @@ class EnableInserterTestCase(FHDLTestCase):
mem = Memory(width=8, depth=4)
f = EnableInserter(self.c1)(mem.write_port()).elaborate(platform=None)
self.assertRepr(f.named_ports["EN"][0], """
(m (sig c1) (cat (repl (slice (sig mem_w_en) 0:1) 8)) (const 8'd0))
(m
(sig c1)
(cat
(cat
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
(slice (sig mem_w_en) 0:1)
)
)
(const 8'd0)
)
""")

9
tests/test_sim.py
View file

@ -289,8 +289,8 @@ class SimulatorUnitTestCase(FHDLTestCase):
stmt = lambda y, a: [rec.eq(a), y.eq(rec)]
self.assertStatement(stmt, [C(0b101, 3)], C(0b101, 3))
def test_repl(self):
stmt = lambda y, a: y.eq(Repl(a, 3))
def test_replicate(self):
stmt = lambda y, a: y.eq(a.replicate(3))
self.assertStatement(stmt, [C(0b10, 2)], C(0b101010, 6))
def test_array(self):
@ -879,11 +879,6 @@ class SimulatorRegressionTestCase(FHDLTestCase):
dut.d.comb += Signal().eq(Cat())
Simulator(dut).run()
def test_bug_325_bis(self):
dut = Module()
dut.d.comb += Signal().eq(Repl(Const(1), 0))
Simulator(dut).run()
def test_bug_473(self):
sim = Simulator(Module())
def process():