back.rtlil: Opportunistically trim zero and sign extension on operands.
Fixes #1148.
This commit is contained in:
Wanda
Catherine
parent
2d59242bf7
commit
d3c5b958d3
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@ -744,6 +744,16 @@ class ModuleEmitter:
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emit_assignments(proc, _nir.Net.from_const(1))
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emit_assignments(proc, _nir.Net.from_const(1))
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assert pos == len(cell.assignments)
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assert pos == len(cell.assignments)
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def shorten_operand(self, value, *, signed):
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value = list(value)
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if signed:
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while len(value) > 1 and value[-1] == value[-2]:
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value.pop()
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else:
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while len(value) > 0 and value[-1] == _nir.Net.from_const(0):
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value.pop()
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return _nir.Value(value)
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def emit_operator(self, cell_idx, cell):
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def emit_operator(self, cell_idx, cell):
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UNARY_OPERATORS = {
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UNARY_OPERATORS = {
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"-": "$neg",
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"-": "$neg",
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@ -782,17 +792,75 @@ class ModuleEmitter:
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if len(cell.inputs) == 1:
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if len(cell.inputs) == 1:
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cell_type = UNARY_OPERATORS[cell.operator]
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cell_type = UNARY_OPERATORS[cell.operator]
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operand, = cell.inputs
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operand, = cell.inputs
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signed = False
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if cell.operator == "-":
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# For arithmetic operands, we trim the extra sign or zero extension on the operands
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# to make the output prettier, and to fix inference problems in some not very smart
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# synthesis tools.
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operand_u = self.shorten_operand(operand, signed=False)
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operand_s = self.shorten_operand(operand, signed=True)
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# The operator will work when lowered with either signedness. Pick whichever
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# is prettier.
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if len(operand_s) < len(operand_u):
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signed = True
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operand = operand_s
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else:
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signed = False
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operand = operand_u
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self.builder.cell(cell_type, ports={
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self.builder.cell(cell_type, ports={
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"A": self.sigspec(operand),
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"A": self.sigspec(operand),
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"Y": self.cell_wires[cell_idx].name
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"Y": self.cell_wires[cell_idx].name
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}, parameters={
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}, parameters={
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"A_SIGNED": False,
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"A_SIGNED": signed,
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"A_WIDTH": len(operand),
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"A_WIDTH": len(operand),
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"Y_WIDTH": cell.width,
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"Y_WIDTH": cell.width,
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}, src_loc=cell.src_loc)
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}, src_loc=cell.src_loc)
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elif len(cell.inputs) == 2:
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elif len(cell.inputs) == 2:
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cell_type, a_signed, b_signed = BINARY_OPERATORS[cell.operator]
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cell_type, a_signed, b_signed = BINARY_OPERATORS[cell.operator]
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operand_a, operand_b = cell.inputs
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operand_a, operand_b = cell.inputs
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if cell.operator in ("+", "-", "*", "==", "!="):
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# Arithmetic operators that will work with any signedness, but we have to choose
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# a common one for both operands. Prefer signed in case of mixed signedness.
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operand_a_u = self.shorten_operand(operand_a, signed=False)
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operand_b_u = self.shorten_operand(operand_b, signed=False)
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operand_a_s = self.shorten_operand(operand_a, signed=True)
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operand_b_s = self.shorten_operand(operand_b, signed=True)
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if operand_a.is_const:
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# In case of constant operand, choose whichever shortens the other one better.
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signed = len(operand_b_s) < len(operand_b_u)
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elif operand_b.is_const:
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signed = len(operand_a_s) < len(operand_a_u)
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elif (len(operand_a_s) < len(operand_a) and len(operand_a_u) == len(operand_a)):
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# Operand A can only be shortened by signed. Pick it.
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signed = True
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elif (len(operand_b_s) < len(operand_b) and len(operand_b_u) == len(operand_b)):
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# Operand B can only be shortened by signed. Pick it.
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signed = True
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else:
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# Otherwise, use unsigned shortening.
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signed = False
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if signed:
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operand_a = operand_a_s
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operand_b = operand_b_s
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else:
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operand_a = operand_a_u
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operand_b = operand_b_u
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a_signed = b_signed = signed
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if cell.operator[0] in "us":
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# Signedness forced, just shorten.
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operand_a = self.shorten_operand(operand_a, signed=a_signed)
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operand_b = self.shorten_operand(operand_b, signed=b_signed)
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if cell.operator == "<<":
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# We can pick the signedness for left operand, but right is fixed.
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operand_a_u = self.shorten_operand(operand_a, signed=False)
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operand_a_s = self.shorten_operand(operand_a, signed=True)
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if len(operand_a_s) < len(operand_a_u):
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a_signed = True
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operand_a = operand_a_s
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else:
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a_signed = False
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operand_a = operand_a_u
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operand_b = self.shorten_operand(operand_b, signed=b_signed)
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if cell.operator in ("u//", "s//", "u%", "s%"):
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if cell.operator in ("u//", "s//", "u%", "s%"):
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result = self.builder.wire(cell.width)
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result = self.builder.wire(cell.width)
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self.builder.cell(cell_type, ports={
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self.builder.cell(cell_type, ports={
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@ -161,6 +161,10 @@ class Value(tuple):
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else:
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else:
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return f"(cat {' '.join(chunks)})"
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return f"(cat {' '.join(chunks)})"
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@property
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def is_const(self):
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return all(net.is_const for net in self)
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__str__ = __repr__
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__str__ = __repr__
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@ -123,16 +123,16 @@ class RHSTestCase(RTLILTestCase):
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wire width 1 $8
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wire width 1 $8
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cell $neg $9
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cell $neg $9
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parameter \A_SIGNED 0
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parameter \A_SIGNED 0
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { 1'0 \i8u [7:0] }
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connect \A \i8u [7:0]
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connect \Y $1
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connect \Y $1
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end
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end
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cell $neg $10
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cell $neg $10
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { \i8s [7] \i8s [7:0] }
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connect \A \i8s [7:0]
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connect \Y $2
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connect \Y $2
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end
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end
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cell $not $11
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cell $not $11
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@ -229,61 +229,61 @@ class RHSTestCase(RTLILTestCase):
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cell $add $5
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cell $add $5
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parameter \A_SIGNED 0
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \B_WIDTH 9
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { 1'0 \i8ua [7:0] }
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connect \A \i8ua [7:0]
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connect \B { 1'0 \i8ub [7:0] }
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connect \B \i8ub [7:0]
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connect \Y $1
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connect \Y $1
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end
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end
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cell $add $6
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cell $add $6
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 10
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parameter \A_WIDTH 9
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parameter \B_WIDTH 10
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 10
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parameter \Y_WIDTH 10
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connect \A { 2'00 \i8ua [7:0] }
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connect \A { 1'0 \i8ua [7:0] }
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connect \B { \i8sb [7] \i8sb [7] \i8sb [7:0] }
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connect \B \i8sb [7:0]
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connect \Y \o2
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connect \Y \o2
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end
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end
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cell $add $7
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cell $add $7
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \B_WIDTH 9
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { \i8sa [7] \i8sa [7:0] }
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connect \A \i8sa [7:0]
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connect \B { \i8sb [7] \i8sb [7:0] }
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connect \B \i8sb [7:0]
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connect \Y $2
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connect \Y $2
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end
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end
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cell $sub $8
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cell $sub $8
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parameter \A_SIGNED 0
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \B_WIDTH 9
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { 1'0 \i8ua [7:0] }
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connect \A \i8ua [7:0]
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connect \B { 1'0 \i8ub [7:0] }
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connect \B \i8ub [7:0]
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connect \Y $3
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connect \Y $3
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end
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end
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cell $sub $9
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cell $sub $9
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 10
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parameter \A_WIDTH 9
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parameter \B_WIDTH 10
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 10
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parameter \Y_WIDTH 10
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connect \A { 2'00 \i8ua [7:0] }
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connect \A { 1'0 \i8ua [7:0] }
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connect \B { \i8sb [7] \i8sb [7] \i8sb [7:0] }
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connect \B \i8sb [7:0]
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connect \Y \o5
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connect \Y \o5
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end
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end
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cell $sub $10
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cell $sub $10
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 9
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parameter \A_WIDTH 8
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parameter \B_WIDTH 9
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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parameter \Y_WIDTH 9
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connect \A { \i8sa [7] \i8sa [7:0] }
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connect \A \i8sa [7:0]
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connect \B { \i8sb [7] \i8sb [7:0] }
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connect \B \i8sb [7:0]
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connect \Y $4
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connect \Y $4
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end
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end
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connect \o1 { 1'0 $1 [8:0] }
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connect \o1 { 1'0 $1 [8:0] }
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@ -293,6 +293,82 @@ class RHSTestCase(RTLILTestCase):
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end
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end
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""")
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""")
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def test_operator_add_imm(self):
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i8u = Signal(8)
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i8s = Signal(signed(8))
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o1 = Signal(10)
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o2 = Signal(10)
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o3 = Signal(10)
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o4 = Signal(10)
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m = Module()
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m.d.comb += [
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o1.eq(i8u + 3),
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o2.eq(i8s + 3),
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o3.eq(3 + i8u),
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o4.eq(3 + i8s),
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]
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self.assertRTLIL(m, [i8u, i8s, o1, o2, o3, o4], R"""
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attribute \generator "Amaranth"
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attribute \top 1
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module \top
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wire width 8 input 0 \i8u
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wire width 8 input 1 signed \i8s
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wire width 10 output 2 \o1
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wire width 10 output 3 \o2
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wire width 10 output 4 \o3
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wire width 10 output 5 \o4
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wire width 9 $1
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wire width 9 $2
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wire width 9 $3
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wire width 9 $4
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cell $add $5
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 2
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parameter \Y_WIDTH 9
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connect \A \i8u [7:0]
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connect \B 2'11
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connect \Y $1
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end
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cell $add $6
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parameter \A_SIGNED 1
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parameter \B_SIGNED 1
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parameter \A_WIDTH 8
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parameter \B_WIDTH 3
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parameter \Y_WIDTH 9
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connect \A \i8s [7:0]
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connect \B 3'011
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connect \Y $2
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end
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cell $add $7
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 2
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A 2'11
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connect \B \i8u [7:0]
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connect \Y $3
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end
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cell $add $8
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parameter \A_SIGNED 1
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parameter \B_SIGNED 1
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parameter \A_WIDTH 3
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A 3'011
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connect \B \i8s [7:0]
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connect \Y $4
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end
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connect \o1 { 1'0 $1 [8:0] }
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connect \o2 { $2 [8] $2 [8:0] }
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connect \o3 { 1'0 $3 [8:0] }
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connect \o4 { $4 [8] $4 [8:0] }
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end
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""")
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def test_operator_mul(self):
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def test_operator_mul(self):
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i4ua = Signal(4)
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i4ua = Signal(4)
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i4ub = Signal(4)
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i4ub = Signal(4)
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@ -324,31 +400,31 @@ class RHSTestCase(RTLILTestCase):
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cell $mul $4
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cell $mul $4
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parameter \A_SIGNED 0
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \A_WIDTH 4
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parameter \B_WIDTH 8
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A { 4'0000 \i4ua [3:0] }
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connect \A \i4ua [3:0]
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connect \B { 4'0000 \i4ub [3:0] }
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connect \B \i4ub [3:0]
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connect \Y $1
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connect \Y $1
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end
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end
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cell $mul $5
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cell $mul $5
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 8
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parameter \A_WIDTH 5
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parameter \B_WIDTH 8
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A { 4'0000 \i4ua [3:0] }
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connect \A { 1'0 \i4ua [3:0] }
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connect \B { \i4sb [3] \i4sb [3] \i4sb [3] \i4sb [3] \i4sb [3:0] }
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connect \B \i4sb [3:0]
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connect \Y $2
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connect \Y $2
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end
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end
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cell $mul $6
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cell $mul $6
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parameter \A_SIGNED 0
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \B_SIGNED 1
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parameter \A_WIDTH 8
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parameter \A_WIDTH 4
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parameter \B_WIDTH 8
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A { \i4sa [3] \i4sa [3] \i4sa [3] \i4sa [3] \i4sa [3:0] }
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connect \A \i4sa [3:0]
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connect \B { \i4sb [3] \i4sb [3] \i4sb [3] \i4sb [3] \i4sb [3:0] }
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connect \B \i4sb [3:0]
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connect \Y $3
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connect \Y $3
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end
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end
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connect \o1 { 1'0 $1 [7:0] }
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connect \o1 { 1'0 $1 [7:0] }
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@ -438,18 +514,18 @@ class RHSTestCase(RTLILTestCase):
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parameter \A_SIGNED 1
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parameter \A_SIGNED 1
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||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 5
|
||||||
parameter \B_WIDTH 5
|
parameter \B_WIDTH 4
|
||||||
parameter \Y_WIDTH 5
|
parameter \Y_WIDTH 5
|
||||||
connect \A { 1'0 \i4ua [3:0] }
|
connect \A { 1'0 \i4ua [3:0] }
|
||||||
connect \B { \i4sb [3] \i4sb [3:0] }
|
connect \B \i4sb [3:0]
|
||||||
connect \Y $14
|
connect \Y $14
|
||||||
end
|
end
|
||||||
wire width 1 $16
|
wire width 1 $16
|
||||||
cell $reduce_bool $17
|
cell $reduce_bool $17
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 0
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \Y_WIDTH 1
|
parameter \Y_WIDTH 1
|
||||||
connect \A { \i4sb [3] \i4sb [3:0] }
|
connect \A \i4sb [3:0]
|
||||||
connect \Y $16
|
connect \Y $16
|
||||||
end
|
end
|
||||||
cell $mux $18
|
cell $mux $18
|
||||||
|
|
@ -464,10 +540,10 @@ class RHSTestCase(RTLILTestCase):
|
||||||
cell $divfloor $20
|
cell $divfloor $20
|
||||||
parameter \A_SIGNED 1
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \B_WIDTH 5
|
parameter \B_WIDTH 5
|
||||||
parameter \Y_WIDTH 5
|
parameter \Y_WIDTH 5
|
||||||
connect \A { \i4sa [3] \i4sa [3:0] }
|
connect \A \i4sa [3:0]
|
||||||
connect \B { 1'0 \i4ub [3:0] }
|
connect \B { 1'0 \i4ub [3:0] }
|
||||||
connect \Y $19
|
connect \Y $19
|
||||||
end
|
end
|
||||||
|
|
@ -491,19 +567,19 @@ class RHSTestCase(RTLILTestCase):
|
||||||
cell $divfloor $25
|
cell $divfloor $25
|
||||||
parameter \A_SIGNED 1
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \B_WIDTH 5
|
parameter \B_WIDTH 4
|
||||||
parameter \Y_WIDTH 5
|
parameter \Y_WIDTH 5
|
||||||
connect \A { \i4sa [3] \i4sa [3:0] }
|
connect \A \i4sa [3:0]
|
||||||
connect \B { \i4sb [3] \i4sb [3:0] }
|
connect \B \i4sb [3:0]
|
||||||
connect \Y $24
|
connect \Y $24
|
||||||
end
|
end
|
||||||
wire width 1 $26
|
wire width 1 $26
|
||||||
cell $reduce_bool $27
|
cell $reduce_bool $27
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 0
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \Y_WIDTH 1
|
parameter \Y_WIDTH 1
|
||||||
connect \A { \i4sb [3] \i4sb [3:0] }
|
connect \A \i4sb [3:0]
|
||||||
connect \Y $26
|
connect \Y $26
|
||||||
end
|
end
|
||||||
cell $mux $28
|
cell $mux $28
|
||||||
|
|
@ -546,18 +622,18 @@ class RHSTestCase(RTLILTestCase):
|
||||||
parameter \A_SIGNED 1
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 5
|
||||||
parameter \B_WIDTH 5
|
parameter \B_WIDTH 4
|
||||||
parameter \Y_WIDTH 5
|
parameter \Y_WIDTH 5
|
||||||
connect \A { 1'0 \i4ua [3:0] }
|
connect \A { 1'0 \i4ua [3:0] }
|
||||||
connect \B { \i4sb [3] \i4sb [3:0] }
|
connect \B \i4sb [3:0]
|
||||||
connect \Y $34
|
connect \Y $34
|
||||||
end
|
end
|
||||||
wire width 1 $36
|
wire width 1 $36
|
||||||
cell $reduce_bool $37
|
cell $reduce_bool $37
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 0
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \Y_WIDTH 1
|
parameter \Y_WIDTH 1
|
||||||
connect \A { \i4sb [3] \i4sb [3:0] }
|
connect \A \i4sb [3:0]
|
||||||
connect \Y $36
|
connect \Y $36
|
||||||
end
|
end
|
||||||
cell $mux $38
|
cell $mux $38
|
||||||
|
|
@ -572,10 +648,10 @@ class RHSTestCase(RTLILTestCase):
|
||||||
cell $modfloor $40
|
cell $modfloor $40
|
||||||
parameter \A_SIGNED 1
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 5
|
parameter \A_WIDTH 4
|
||||||
parameter \B_WIDTH 5
|
parameter \B_WIDTH 5
|
||||||
parameter \Y_WIDTH 5
|
parameter \Y_WIDTH 5
|
||||||
connect \A { \i4sa [3] \i4sa [3:0] }
|
connect \A \i4sa [3:0]
|
||||||
connect \B { 1'0 \i4ub [3:0] }
|
connect \B { 1'0 \i4ub [3:0] }
|
||||||
connect \Y $39
|
connect \Y $39
|
||||||
end
|
end
|
||||||
|
|
@ -666,20 +742,20 @@ class RHSTestCase(RTLILTestCase):
|
||||||
cell $shl $5
|
cell $shl $5
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 0
|
||||||
parameter \B_SIGNED 0
|
parameter \B_SIGNED 0
|
||||||
parameter \A_WIDTH 15
|
parameter \A_WIDTH 8
|
||||||
parameter \B_WIDTH 3
|
parameter \B_WIDTH 3
|
||||||
parameter \Y_WIDTH 15
|
parameter \Y_WIDTH 15
|
||||||
connect \A { 7'0000000 \i8ua [7:0] }
|
connect \A \i8ua [7:0]
|
||||||
connect \B \i3 [2:0]
|
connect \B \i3 [2:0]
|
||||||
connect \Y $1
|
connect \Y $1
|
||||||
end
|
end
|
||||||
cell $shl $6
|
cell $shl $6
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 0
|
parameter \B_SIGNED 0
|
||||||
parameter \A_WIDTH 15
|
parameter \A_WIDTH 8
|
||||||
parameter \B_WIDTH 3
|
parameter \B_WIDTH 3
|
||||||
parameter \Y_WIDTH 15
|
parameter \Y_WIDTH 15
|
||||||
connect \A { \i8sa [7] \i8sa [7] \i8sa [7] \i8sa [7] \i8sa [7] \i8sa [7] \i8sa [7] \i8sa [7:0] }
|
connect \A \i8sa [7:0]
|
||||||
connect \B \i3 [2:0]
|
connect \B \i3 [2:0]
|
||||||
connect \Y $2
|
connect \Y $2
|
||||||
end
|
end
|
||||||
|
|
@ -822,13 +898,13 @@ class RHSTestCase(RTLILTestCase):
|
||||||
connect \Y $1
|
connect \Y $1
|
||||||
end
|
end
|
||||||
cell $eqop $5
|
cell $eqop $5
|
||||||
parameter \A_SIGNED 0
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 0
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 9
|
parameter \A_WIDTH 9
|
||||||
parameter \B_WIDTH 9
|
parameter \B_WIDTH 8
|
||||||
parameter \Y_WIDTH 1
|
parameter \Y_WIDTH 1
|
||||||
connect \A { 1'0 \i8ua [7:0] }
|
connect \A { 1'0 \i8ua [7:0] }
|
||||||
connect \B { \i8sb [7] \i8sb [7:0] }
|
connect \B \i8sb [7:0]
|
||||||
connect \Y $2
|
connect \Y $2
|
||||||
end
|
end
|
||||||
cell $eqop $6
|
cell $eqop $6
|
||||||
|
|
@ -895,10 +971,10 @@ class RHSTestCase(RTLILTestCase):
|
||||||
parameter \A_SIGNED 1
|
parameter \A_SIGNED 1
|
||||||
parameter \B_SIGNED 1
|
parameter \B_SIGNED 1
|
||||||
parameter \A_WIDTH 9
|
parameter \A_WIDTH 9
|
||||||
parameter \B_WIDTH 9
|
parameter \B_WIDTH 8
|
||||||
parameter \Y_WIDTH 1
|
parameter \Y_WIDTH 1
|
||||||
connect \A { 1'0 \i8ua [7:0] }
|
connect \A { 1'0 \i8ua [7:0] }
|
||||||
connect \B { \i8sb [7] \i8sb [7:0] }
|
connect \B \i8sb [7:0]
|
||||||
connect \Y $2
|
connect \Y $2
|
||||||
end
|
end
|
||||||
cell $cmpop $6
|
cell $cmpop $6
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue