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back.pysim: more general clean-up.

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This commit is contained in:
whitequark 2018-12-14 12:42:39 +00:00
parent 1b7f8c7950
commit dd00b5e2d6
3 changed files with 45 additions and 38 deletions
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7
examples/clkdiv.py
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@ -20,6 +20,7 @@ frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o]))
print(verilog.convert(frag, ports=[ctr.o]))
sim = pysim.Simulator(frag, vcd_file=open("clkdiv.vcd", "w"))
sim.add_clock("sync", 1e-6)
with sim: sim.run_until(100e-6, run_passive=True)
with pysim.Simulator(frag,
vcd_file=open("clkdiv.vcd", "w")) as sim:
sim.add_clock(1e-6)
sim.run_until(100e-6, run_passive=True)

28
examples/ctrl.py
View file

@ -21,17 +21,17 @@ frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
sim = pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o])
sim.add_clock("sync", 1e-6)
def ce_proc():
yield; yield; yield
yield ctr.ce.eq(1)
yield; yield; yield
yield ctr.ce.eq(0)
yield; yield; yield
yield ctr.ce.eq(1)
sim.add_sync_process(ce_proc())
with sim: sim.run_until(100e-6, run_passive=True)
with pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
sim.add_clock(1e-6)
def ce_proc():
yield; yield; yield
yield ctr.ce.eq(1)
yield; yield; yield
yield ctr.ce.eq(0)
yield; yield; yield
yield ctr.ce.eq(1)
sim.add_sync_process(ce_proc())
sim.run_until(100e-6, run_passive=True)