sim: add eval_format function.

This will be used in an upcoming PR for VCD output.

amaranth/sim/_pyeval.py

@@ -128,6 +128,33 @@ def eval_value(sim, value):
         assert False # :nocov:
 
 
+def value_to_string(value):
+    """Unpack a Verilog-like (but LSB-first) string of unknown width from an integer."""
+    msg = bytearray()
+    while value:
+        byte = value & 0xff
+        value >>= 8
+        if byte:
+            msg.append(byte)
+    return msg.decode()
+
+
+def eval_format(sim, fmt):
+    fmt = Format("{}", fmt)
+    chunks = []
+    for chunk in fmt._chunks:
+        if isinstance(chunk, str):
+            chunks.append(chunk)
+        else:
+            value, spec = chunk
+            value = eval_value(sim, value)
+            if spec.endswith("s"):
+                chunks.append(format(value_to_string(value), spec[:-1]))
+            else:
+                chunks.append(format(value, spec))
+    return "".join(chunks)
+
+
 def _eval_assign_inner(sim, lhs, lhs_start, rhs, rhs_len):
     if isinstance(lhs, Operator) and lhs.operator in ("u", "s"):
         _eval_assign_inner(sim, lhs.operands[0], lhs_start, rhs, rhs_len)

amaranth/sim/_pyrtl.py

@@ -8,6 +8,7 @@ from ..hdl._ast import SignalSet, _StatementList, Property
 from ..hdl._xfrm import ValueVisitor, StatementVisitor
 from ..hdl._mem import MemoryInstance
 from ._base import BaseProcess
+from ._pyeval import value_to_string
 
 
 __all__ = ["PyRTLProcess"]
@@ -356,17 +357,6 @@ class _LHSValueCompiler(_ValueCompiler):
         return gen
 
 
-def value_to_string(value):
-    """Unpack a Verilog-like (but LSB-first) string of unknown width from an integer."""
-    msg = bytearray()
-    while value:
-        byte = value & 0xff
-        value >>= 8
-        if byte:
-            msg.append(byte)
-    return msg.decode()
-
-
 def pin_blame(src_loc, exc):
     if src_loc is None:
         raise exc