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sim: raise an exception on add_clock conflict with comb driver.

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Wanda 2024-06-14 19:34:19 +02:00 committed by Catherine
parent 66ad0a207e
commit f5a8c07d54
2 changed files with 13 additions and 0 deletions
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4
amaranth/sim/pysim.py
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@ -616,6 +616,10 @@ class PySimEngine(BaseEngine):
testbench.reset() testbench.reset()
def add_clock_process(self, clock, *, phase, period): def add_clock_process(self, clock, *, phase, period):
slot = self.state.get_signal(clock)
if self.state.slots[slot].is_comb:
raise DriverConflict("Clock signal is already driven by combinational logic")
self._processes.add(PyClockProcess(self._state, clock, self._processes.add(PyClockProcess(self._state, clock,
phase=phase, period=period)) phase=phase, period=period))

9
tests/test_sim.py
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@ -1497,6 +1497,15 @@ class SimulatorRegressionTestCase(FHDLTestCase):
sim.add_testbench(testbench) sim.add_testbench(testbench)
sim.run() sim.run()
def test_comb_clock_conflict(self):
c = Signal()
m = Module()
m.d.comb += ClockSignal().eq(c)
sim = Simulator(m)
with self.assertRaisesRegex(DriverConflict,
r"^Clock signal is already driven by combinational logic$"):
sim.add_clock(1e-6)
def test_sample(self): def test_sample(self):
m = Module() m = Module()
m.domains.sync = cd_sync = ClockDomain() m.domains.sync = cd_sync = ClockDomain()