whitequark
parent
9d2cbbabb8
commit
fa0fa056ba
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@ -38,8 +38,8 @@ Compatibility summary
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<br>Note: `transform_*` methods not considered part of public API.
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- (⊙) `ModuleTransformer` **brk**
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- (⊙) `ControlInserter` **brk**
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- (-) `CEInserter` **obs**
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- (-) `ResetInserter` **obs**
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- (+) `CEInserter` → `EnableInserter`
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- (+) `ResetInserter` id
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- (+) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=`
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- (⊙) `edif` **brk**
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- (+) `module` **obs** → `.hdl.dsl`
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@ -6,30 +6,30 @@ class Counter(Elaboratable):
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def __init__(self, width):
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self.v = Signal(width, reset=2**width-1)
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self.o = Signal()
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self.ce = Signal()
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self.en = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return CEInserter(self.ce)(m)
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return EnableInserter(self.en)(m)
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ctr = Counter(width=16)
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print(verilog.convert(ctr, ports=[ctr.o, ctr.ce]))
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print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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with pysim.Simulator(ctr,
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vcd_file=open("ctrl.vcd", "w"),
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gtkw_file=open("ctrl.gtkw", "w"),
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traces=[ctr.ce, ctr.v, ctr.o]) as sim:
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traces=[ctr.en, ctr.v, ctr.o]) as sim:
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield ctr.ce.eq(1)
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yield ctr.en.eq(1)
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yield; yield; yield
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yield ctr.ce.eq(0)
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yield ctr.en.eq(0)
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yield; yield; yield
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yield ctr.ce.eq(1)
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yield ctr.en.eq(1)
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sim.add_sync_process(ce_proc())
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sim.run_until(100e-6, run_passive=True)
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@ -4,4 +4,5 @@ from .cd import ClockDomain
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from .ir import Elaboratable, Fragment, Instance
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from .mem import Memory
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from .rec import Record
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from .xfrm import DomainRenamer, ResetInserter, CEInserter
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from .xfrm import DomainRenamer, ResetInserter, EnableInserter, \
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CEInserter # deprecated
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@ -2,7 +2,7 @@ from abc import ABCMeta, abstractmethod
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from collections import OrderedDict
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from collections.abc import Iterable
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from ..tools import flatten
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from ..tools import flatten, deprecated
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from .. import tracer
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from .ast import *
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from .ast import _StatementList
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@ -18,7 +18,7 @@ __all__ = ["ValueVisitor", "ValueTransformer",
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"DomainCollector", "DomainRenamer", "DomainLowerer",
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"SampleDomainInjector", "SampleLowerer",
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"SwitchCleaner", "LHSGroupAnalyzer", "LHSGroupFilter",
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"ResetInserter", "CEInserter"]
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"ResetInserter", "EnableInserter", "CEInserter"]
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class ValueVisitor(metaclass=ABCMeta):
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@ -657,7 +657,7 @@ class ResetInserter(_ControlInserter):
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fragment.add_statements(Switch(self.controls[domain], {1: stmts}, src_loc=self.src_loc))
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class CEInserter(_ControlInserter):
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class EnableInserter(_ControlInserter):
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def _insert_control(self, fragment, domain, signals):
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stmts = [s.eq(s) for s in signals]
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fragment.add_statements(Switch(self.controls[domain], {0: stmts}, src_loc=self.src_loc))
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@ -671,3 +671,6 @@ class CEInserter(_ControlInserter):
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en_port = Mux(self.controls[clk_port.domain], en_port, Const(0, len(en_port)))
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new_fragment.named_ports["EN"] = en_port, en_dir
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return new_fragment
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CEInserter = deprecated("instead of `CEInserter`, use `EnableInserter`")(EnableInserter)
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@ -18,7 +18,7 @@ class ExamplesTestCase(FHDLTestCase):
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test_arst = example_test("basic/arst.py")
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test_cdc = example_test("basic/cdc.py")
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test_ctr = example_test("basic/ctr.py")
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test_ctr_ce = example_test("basic/ctr_ce.py")
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test_ctr_en = example_test("basic/ctr_en.py")
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test_fsm = example_test("basic/fsm.py")
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test_gpio = example_test("basic/gpio.py")
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test_inst = example_test("basic/inst.py")
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@ -437,21 +437,21 @@ class ResetInserterTestCase(FHDLTestCase):
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""")
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class CEInserterTestCase(FHDLTestCase):
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class EnableInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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def test_ce_default(self):
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def test_enable_default(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1)
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)
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f.add_driver(self.s1, "sync")
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f = CEInserter(self.c1)(f)
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f = EnableInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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@ -461,7 +461,7 @@ class CEInserterTestCase(FHDLTestCase):
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)
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""")
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def test_ce_cd(self):
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def test_enable_cd(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1),
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@ -470,7 +470,7 @@ class CEInserterTestCase(FHDLTestCase):
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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f = CEInserter({"pix": self.c1})(f)
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f = EnableInserter({"pix": self.c1})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (const 1'd1))
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@ -481,7 +481,7 @@ class CEInserterTestCase(FHDLTestCase):
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)
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""")
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def test_ce_subfragment(self):
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def test_enable_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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self.s1.eq(1)
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@ -495,7 +495,7 @@ class CEInserterTestCase(FHDLTestCase):
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f2.add_driver(self.s2, "sync")
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f1.add_subfragment(f2)
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f1 = CEInserter(self.c1)(f1)
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f1 = EnableInserter(self.c1)(f1)
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(f2, _), = f1.subfragments
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self.assertRepr(f1.statements, """
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(
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@ -514,16 +514,16 @@ class CEInserterTestCase(FHDLTestCase):
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)
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""")
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def test_ce_read_port(self):
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def test_enable_read_port(self):
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mem = Memory(width=8, depth=4)
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f = CEInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None)
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f = EnableInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None)
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self.assertRepr(f.named_ports["EN"][0], """
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(m (sig c1) (sig mem_r_en) (const 1'd0))
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""")
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def test_ce_write_port(self):
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def test_enable_write_port(self):
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mem = Memory(width=8, depth=4)
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f = CEInserter(self.c1)(mem.write_port()).elaborate(platform=None)
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f = EnableInserter(self.c1)(mem.write_port()).elaborate(platform=None)
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self.assertRepr(f.named_ports["EN"][0], """
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(m (sig c1) (cat (repl (slice (sig mem_w_en) 0:1) 8)) (const 8'd0))
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""")
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@ -549,13 +549,13 @@ class TransformedElaboratableTestCase(FHDLTestCase):
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def test_getattr(self):
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e = _MockElaboratable()
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te = CEInserter(self.c1)(e)
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te = EnableInserter(self.c1)(e)
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self.assertIs(te.s1, e.s1)
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def test_composition(self):
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e = _MockElaboratable()
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te1 = CEInserter(self.c1)(e)
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te1 = EnableInserter(self.c1)(e)
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te2 = ResetInserter(self.c2)(te1)
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self.assertIsInstance(te1, TransformedElaboratable)
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